参数资料
型号: LTC3553EUD#PBF
厂商: LINEAR TECHNOLOGY CORP
元件分类: 电源管理
英文描述: 1-CHANNEL POWER SUPPLY SUPPORT CKT, PQCC20
封装: 3 X 3 MM, 0.75 MM HEIGHT, LEAD FREE, PLASTIC, QFN-20
文件页数: 16/36页
文件大小: 518K
代理商: LTC3553EUD#PBF
LTC3553
23
3553fa
The switching regulator input supply should be bypassed
with a 2.2μF capacitor. Consult with capacitor manufac-
turers for detailed information on their selection and
specications of ceramic capacitors. Many manufacturers
now offer very thin (<1mm tall) ceramic capacitors ideal
for use in height-restricted designs. Table 2 shows a list
of several ceramic capacitor manufacturers.
LOW DROPOUT LINEAR REGULATOR (LDO)
The LDO regulator supports a load of up to 150mA. The
LDO takes power from the VINLDO pin and drives the LDO
output pin with the goal of bringing the LDO_FB feedback
pin voltage to 0.8V. Usually, a resistor divider is connected
between the LDO’s output pin, feedback pin and ground,
in order to close the control loop and program the output
voltage. For stability, the LDO output must be bypassed
to ground with at least a 1μF ceramic capacitor.
The LDO is enabled or disabled via the pushbutton interface.
In cases where the LDO is disabled and the PowerPath
is actively driving VOUT, an internal pull-down resistor is
switched in to help bring the output to ground. When the
LDO is enabled, a soft-start circuit ramps its regulation
point from zero to nal value over a period of roughly
0.2ms, reducing the required VINLDO inrush current.
The LDO has two input voltage requirements. The LDO’s
quiescent bias current is supplied through an internal
connection to the USB PowerPath VOUT pin. The LDO’s
power input is taken from the VINLDO pin. For proper
LDO operation, the VINLDO pin must be connected to a
voltage no greater than VOUT. For example, VINLDO can
OPERATION
be connected to VOUT, or to the buck regulator output.
Connecting VINLDO to a voltage exceeding VOUT may result
in loss of regulation.
Output Voltage Programming
Figure 4 shows the LDO regulator application circuit.
Program the LDO output voltage, VLDO, by choosing R1
and R2 such that:
V
LDO = 0.8V
R1
R2
+1
Standby Mode LDO Operation (STBY Pin High)
To reduce battery drain current in applications with a
static memory keep-alive or other ultralow quiescent
current state, the LDO may be placed into standby mode
COUT
LDO
OUTPUT
LDO_FB
LDO
MP
0.8V
R2
GND
R1
0
1
3553 F04
LDO
ENABLE
VINLDO
Figure 4. LDO Application Circuit
相关PDF资料
PDF描述
LTC3554EPD#TRPB 0.5 A BATTERY CHARGE CONTROLLER, 1295 kHz SWITCHING FREQ-MAX, PQCC20
LTC3560IS6#TRPBF 2.1 A SWITCHING REGULATOR, 2700 kHz SWITCHING FREQ-MAX, PDSO6
LTC3563EDC 1.75 A SWITCHING REGULATOR, 2700 kHz SWITCHING FREQ-MAX, PDSO6
LTC3568EDD#TR 4 A SWITCHING REGULATOR, 4000 kHz SWITCHING FREQ-MAX, PDSO10
LTC3568IDD 4 A SWITCHING REGULATOR, 4000 kHz SWITCHING FREQ-MAX, PDSO10
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