参数资料
型号: LTC3553EUD#PBF
厂商: LINEAR TECHNOLOGY CORP
元件分类: 电源管理
英文描述: 1-CHANNEL POWER SUPPLY SUPPORT CKT, PQCC20
封装: 3 X 3 MM, 0.75 MM HEIGHT, LEAD FREE, PLASTIC, QFN-20
文件页数: 21/36页
文件大小: 518K
代理商: LTC3553EUD#PBF
LTC3553
28
3553fa
the application up and down for housekeeping and other
activities not needing the user’s control.
Power-Down by De-Asserting Both BUCK_ON and
LDO_ON
Figure 11 shows the LTC3553 powering down by μC/μP
control. For this example the pushbutton circuitry starts in
the PON state with a battery connected and both regula-
tors enabled. The user presses the pushbutton (ON low)
for at least 50ms, which generates a debounced, low
impedance pulse on the PBSTAT output. After receiving
the PBSTAT signal, the μC/μP software decides to drive
both the BUCK_ON and LDO_ON inputs low in order to
power down. After the last input goes low, the pushbutton
circuitry will enter the PDN2 state. In the PDN2 state a one
second wait time is initiated after which the pushbutton
circuitry enters the POFF state. During this one second
time, the ON, BUCK_ON and LDO_ON inputs as well as
external power application are ignored to allow all LTC3553
OPERATION
generated supplies to go low. Though the above assumes
a battery present, the same operation would take place
with a valid external supply (VBUS) with or without a bat-
tery present.
Holding ON low through the one second power-down
period will not cause a power-up event at end of the one
second period. The ON pin must be brought high following
the power-down event and then go low again to establish
a valid power-up event.
UVLO Minimum Off-Time Timing (Low Battery)
Figure 12 assumes the battery is either missing or at a
voltage below the VOUT UVLO threshold, and the appli-
cation is running via external power (VBUS). A glitch on
the external supply causes VOUT to drop below the VOUT
UVLO threshold temporarily. This VOUT UVLO condition
causes the pushbutton circuitry to transition from the PON
state to the PDN2 state. Upon entering the PDN2 state the
regulators power down together.
BAT
VBUS
ON (PB)
PBSTAT
BUCK
LDO
SEQ
BUCK_ON
LDO_ON
STATE
PON
PUP2
PDN2
3553 TD05
5s
1s, BUCK POWERS UP
LDO POWERS UP
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Figure 12. UVLO Minimum Off-Time Timing
BAT
VBUS
ON (PB)
PBSTAT
BUCK
LDO
BUCK_ON
LDO_ON
STATE
PON
POFF
PDN2
3553 TD04
1s
C/P CONTROL
50ms
C/P CONTROL
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Figure 11. Power-Down via De-Assertion of
BUCK_ON and LDO_ON
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