参数资料
型号: LTC3589IUJ-1#PBF
厂商: LINEAR TECHNOLOGY CORP
元件分类: 稳压器
英文描述: SWITCHING REGULATOR, 2600 kHz SWITCHING FREQ-MAX, PQCC40
封装: 6 X 6 MM, 0.75 MM HEIGHT, LEAD FREE, PLASTIC, QFN-40
文件页数: 24/46页
文件大小: 570K
代理商: LTC3589IUJ-1#PBF
LTC3589/LTC3589-1
30
3589fc
Figure12showsthestart-uptimingfortheapplicationshown
in Figure 11. There is a 200μs (typical) delay between the
enable pin and the internal enable signal to each regulator.
Depending on settings in I2C system control register 2
(SCR2), a regulator’s output must discharge to less than
300mV before it will respond to its enable. The output
discharge feature is to guarantee proper start-up sequenc-
ing. This feature and the 2.5k pull-down resistors may be
overridden by bit settings in command register SCR2.
OPERATION
Figure 11. Pin-Strap Start-Up Sequence Application Circuit
3589 F11
EN1
EN2
EN3
EN4
EN_LDO2
EN_LDO34
ON
PWR_ON
LTC3589
PWR_ON
WAKE
SW1
SW2
SW3
BB_OUT
LDO2
LDO3
LDO4
1V TO 1.2V
1.8V
0.8V TO 1V
3.3V
1.2V
1.8V
2.8V
ON(PB)
PBSTAT
FAULT
WAKE
PWR_ON
CLIRQ
IRQ
3589 F10
μC/μP CONTROL
<1 SEC
Figure 10. Hard Reset Due to a Fault Condition
ENABLE AND POWER-ON SEQUENCING
Enable Input Pin Operation
The regulator enable input pins facilitate pin-strapping an
output rail to the enable pin of the next regulator in the
desired sequence. The regulator enable inputs normally
have a 0.8V (typical) input threshold. If any enable is driven
HIGH, the remaining enable input thresholds switch to a
more accurate 500mV (typical) threshold.
Figure 11 shows an application circuit for a typical pin-
strapped start-up sequence. Holding ON LOW for 400ms
brings up the WAKE pin that is tied to EN1 and EN3 to en-
able step-down switching regulators 1 and 3. The output of
regulator 1 is tied to EN2 and EN4 that enables step-down
switchingregulator2andthebuck-boostswitchingregulator
4. The output of step-down switching regulator 2 is tied to
EN_LDO2 and EN_LDO3 to enable LDO2, LDO3 and LDO4.
WithinfivesecondsofWAKEgoingHIGH,themicroprocessor
ormicrocontrollermustdrivePWR_ONHIGHtotellLTC3589
that rails are good and to stay in the power-on state.
Figure 6. Power-Up Using the Pushbutton
PBSTAT
WAKE
PWR_ON
3589 F06
ON(PB)
μC/μP CONTROL
400ms
<5 SEC
PBSTAT
WAKE
PWR_ON
3589 F07
ON(PB)
μC/μP CONTROL
50ms - LTC3589
2ms - LTC3589-1
50ms
<5 SEC
PBSTAT
WAKE
PWR_ON
3589 F08
ON(PB)
μC/μP CONTROL
50ms
5 SEC
50ms - LTC3589
2ms - LTC3589-1
Figure 9. Hard Reset Using the Pushbutton
PBSTAT
WAKE
PWR_ON
RSTO
3589 F09
ON(PB)
μC/μP CONTROL
50ms
1 SEC
5 SEC
Figure 7. Power Down Using Pushbutton
Figure 8. Power-Up and Down Using PWR_ON Pin
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