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| 型号： | LTC3589IUJ-1#PBF |
| 厂商： | LINEAR TECHNOLOGY CORP |
| 元件分类： | 稳压器 |
| 英文描述： | SWITCHING REGULATOR, 2600 kHz SWITCHING FREQ-MAX, PQCC40 |
| 封装： | 6 X 6 MM, 0.75 MM HEIGHT, LEAD FREE, PLASTIC, QFN-40 |
| 文件页数： | 29/46页 |
| 文件大小： | 570K |
| 代理商： | LTC3589IUJ-1#PBF |
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LTC3589/LTC3589-1
35
3589fc
pulls down the SDA line during the write acknowledge
clock pulse so that it is a stable LOW during the HIGH
period of this clock pulse.
I2C Slave Address
The LTC3589/LTC3589-1 responds to factory programmed
read and write addresses. The write address is 0x68. The
read address is 0x69. The least significant bit of the address
byte, known as the read/write bit, is 0 when writing data
to the LTC3589/LTC3589-1 and 1 when reading from it.
I2C Sub-Addressed Writing
The LTC3589/LTC3589-1 has 14 command registers for
control inputs. They are accessed by the I2C port via a
sub-addressed writing system.
Each write cycle of the LTC3589/LTC3589-1 consists of a
series of three or more bytes beginning with the LTC3589/
LTC3589-1 write address. The second byte is the sub
address of the command register being written to. The
sub address is a pointer to the register where the data
in the third byte will be stored. The third byte is the data
to be written to the just-received sub address. Continue
alternating sub address and data bytes to write multiple
registers in a single START sequence.
I2C Bus Write Operation
The master initiates communication with the LTC3589/
LTC3589-1 with a START condition and the LTC3589/
LTC3589-1write address. If the address matches that of
the LTC3589/LTC3589-1, the LTC3589/LTC3589-1 returns
an acknowledge pulse. The master should then deliver the
sub address. Again the LTC3589/LTC3589-1 acknowledges
and the cycle is repeated for the data byte. The data byte
is transferred to an internal holding latch upon the return
of its acknowledge by the LTC3589/LTC3589-1. Continue
writing sub address and data pairs into the holding latches.
Addressing the LTC3589LTC3589-1 is not required for each
sub address and data pair. If desired a REPEAT-START
condition may be initiated by the master where another
device on the I2C bus is addressed. The LTC3589/LTC3589-1
remembers the valid data it has received. Once all the
devices on the I2C have been addressed and sent valid
data and a global STOP has been sent, the LTC3589/
LTC3589-1 will update its command latches with the data
it has received.
I2C Sub-Addressed Reading
The LTC3589/LTC3589-1 I2C interface supports random
address reading of the I2C command and status registers.
Before reading a register, the registers sub address must be
written. Send a START condition followed by the LTC3589/
LTC3589-1 write address followed by the sub address of
the register to be read. The sub address is now stored as
a pointer to the register. Send a REPEAT-START condition
followed by the LTC3589/LTC3589-1 read address. Follow-
ing the acknowledgment of its read address the LTC3589/
LTC3589-1 returns one bit of information for each of the
next 8 clock cycles. A STOP condition is not required for
the read operation. The read sub address is stored until
a new sub address is written.
Verify the data written to the internal data hold latches
prior to committing date to the command registers by
reading back the data before sending a STOP condition.
Continuously poll a register by repeatedly sending a
START condition followed by the LTC3589/LTC3589-1
read address, and then clocking the data out after the read
address acknowledge.
OPERATION
Figure 20. LTC3589 I2C Serial Port Read Pattern
ACK
START
STOP
1
0
23
11
ADDRESS
4
0
5678
000
9
123
45678
9
123
45678
011
01001
9
123
45678
9
1
01
1
0
10
0
WR
START
SDA
SCL
SUB ADDRESS
S7 S6
S3
S4
S5
S2
S1
S0
ADDRESS
01
1
0
10
0
RD
DATA
R7 R6
R3
R4
R5
R2 R1 R0
3589 F20
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