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| 型号： | LTC3589IUJ-1#PBF |
| 厂商： | LINEAR TECHNOLOGY CORP |
| 元件分类： | 稳压器 |
| 英文描述： | SWITCHING REGULATOR, 2600 kHz SWITCHING FREQ-MAX, PQCC40 |
| 封装： | 6 X 6 MM, 0.75 MM HEIGHT, LEAD FREE, PLASTIC, QFN-40 |
| 文件页数： | 36/46页 |
| 文件大小： | 570K |
| 代理商： | LTC3589IUJ-1#PBF |
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LTC3589/LTC3589-1
41
3589fc
OPERATION
APPLICATIONS INFORMATION
The LTC3589/LTC3589-1 is optimized to support several
families of advanced portable applications processors
including the Marvell PXA3xx and PXA168 Xscale proces-
sors, the Freescale i.MX family including the new i.MX51,
the TI OMAP processors utilizing their Smart reflex, and
many additional ARM processors.
PXA3XX Monahans Processor Support
The PXA3XX processors are hard-coded to communicate
with a PMIC at specific command register addresses in
order to power up the processor supply rails from the low
power state. The LTC3589/LTC3589-1 I2C device address
andcommandregisteraddressesmaptoPXA3xxcommand
register sub-address requirements. The LTC3589 write
address is 0x68. The key command register addresses
for PXA3xx support are the Output Voltage Enable (OVEN)
register at address 0x10. VCC_APPS/A_EN is mapped
to OVEN bit 0 (enable step-down switching regulator 1).
VCC_SRAM/S_EN is mapped to OVEN bit 2 (enable step-
down switching regulator 3). The voltage change control
register (VCCR) at command register address 0x20 con-
trols the dynamic voltage select and go bits required to
command a voltage change and slew when coming out
of low voltage standby or sleep modes into run mode.
The dynamic target voltage (xxDTV[1,2]) registers map
to the mandatory command register addresses. The full
register map for the LTC3589 shown in Table 16 and Table
17 supports Monahans, hard-coded I2C commands for
start-of-day operation, voltage-change sequence, supply
enable, and return-to-D0 state sequence.
The LTC3589/LTC3589-1 does not specifically reference
the Monahans SYS_EN and PWR_EN enable pins but
supports these signals with individual enable input pins
EN[1-4] and EN_LDO[2,34] that should be hard-wired to
SYS_EN or PWR_EN as required for proper system-level
power sequencing.
The LTC3589/LTC3589-1 RSTO signal is used to drive the
Monahans hard reset signal nRESET and is based on the
state of the always-active regulator output LDO1_STBY
and by a pushbutton hard reset request. The release of the
RSTO output is delayed a minimum of 10ms as required
or as long as 1s when the LTC3589/LTC3589-1 is reset
using its pushbutton controller.
Printed Circuit Board Layout
When laying out the printed circuit board, the following
checklist should be followed to ensure proper operation
of the LTC3589/LTC3589-1:
1. Connect the exposed pad of the package (Pin 41)
directly to a large ground plane to minimize thermal
and electrical impedance.
2. The switching regulator input supply traces and their
decoupling capacitors should be as short as possible.
Connect the GND side of the capacitors directly to the
ground plane of the board. The decoupling capacitors
provide the AC current to the internal power MOSFETs
and their drivers. It is important to minimize inductance
from the capacitors to the LTC3589/LTC3589-1 pins.
3. Minimize the switching power traces connecting SW1,
SW2, SW3, and buck-boost switch pins SW4AB and
SW4CD to the inductors to reduce radiated EMI and
parasitic coupling. Keep sensitive nodes such as the
feedback pins away from or shielded from the large
voltage swings on the switching nodes.
4. Minimize the length of the connection between the
step-down switching regulator inductors and the output
capacitors. Connect the GND side of the output capaci-
tors directly to the thermal ground plane of the board.
5. Minimize the length of the connection between the
buck-boost regulator output (BB_OUT) and the output
capacitor. Connect the GND side of the output capacitor
directly to the thermal ground plane of the board.
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