参数资料
型号: LTC3709EUH#TRPBF
厂商: Linear Technology
文件页数: 14/24页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM CM 32-QFN
标准包装: 2,500
系列: PolyPhase®
PWM 型: 电流模式
输出数: 1
频率 - 最大: 200kHz
占空比: 90%
电源电压: 5 V ~ 36 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 32-WFQFN 裸露焊盘
包装: 带卷 (TR)
LTC3709
APPLICATIO S I FOR ATIO
A reasonable starting point is to choose a ripple current
that is about 40% of I OUT(MAX) /2. Note that the largest
ripple current occurs at the highest V IN . To guarantee that
In the Figure 2 graph, the local maximum input RMS
capacitor currents are reached when:
ripple current does not exceed a specified maximum, the
inductance should be chosen according to:
V OUT
V IN
=
2 k – 1
4
where k = 1, 2
? ? ?
L = ?
? ? 1 –
V OUT ?
V OUT
? f ? ? I L ( MAX ) ? ?
?
V IN ( MAX ) ?
These worst-case conditions are commonly used for
design because even significant deviations do not offer
much relief. Note that ripple current ratings from capacitor
Once the value for L is known, the inductors must be
selected (based on the RMS saturation current ratings). A
variety of inductors designed for high current, low voltage
applications are available from manufacturers such as
Sumida, Toko and Panasonic.
Schottky Diode Selection
The Schottky diodes conduct during the dead time be-
tween the conduction of the power MOSFET switches. It is
intended to prevent the body diode of the bottom MOSFET
from turning on and storing charge during the dead time,
which causes a modest (about 1%) efficiency loss. The
diode can be rated for about one-half to one-fifth of the full
load current since it is on for only a fraction of the duty
cycle. In order for the diode to be effective, the inductance
between the diode and the bottom MOSFET must be as
small as possible, mandating that these components be
placed adjacently. The diode can be omitted if the effi-
ciency loss is tolerable.
manufacturers are often based on only 2000 hours of life
which makes it advisable to derate the capacitor. Several
capacitors may also be paralleled to meet size or height
requirements in the design. Always consult the capacitor
manufacturer if there is any question.
It is important to note that the efficiency loss is propor-
tional to the input RMS current squared and therefore a
2-stage implementation results in 75% less power loss
when compared to a single phase design. Battery/input
protection fuse resistance (if used), PC board trace and
connector resistance losses are also reduced by the re-
duction of the input ripple current in a 2-phase system. The
required amount of input capacitance is further reduced by
the factor 2 due to the effective increase in the frequency
of the current pulses.
0.6
0.5
C IN and C OUT Selection
In continuous mode, the current of each top N-channel
MOSFET is a square wave of duty cycle V OUT /V IN . A low
ESR input capacitor sized for the maximum RMS current
must be used. The details of a close form equation can be
0.4
0.3
0.2
0.1
1-PHASE
2-PHASE
found in Application Note 77. Figure 2 shows the input
capacitor ripple current for a 2-phase configuration with
0
0.1
0.2
0.3 0.4 0.5 0.6 0.7
DUTY FACTOR (V OUT /V IN )
0.8
0.9
the output voltage fixed and input voltage varied. The input
ripple current is normalized against the DC output current.
3709 F02
Figure 2. RMS Input Current Comparison
The graph can be used in place of tedious calculations. The
minimum input ripple current can be achieved when the
input voltage is twice the output voltage.
3709fb
14
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