参数资料
型号: LTC3730CG#TR
厂商: Linear Technology
文件页数: 14/28页
文件大小: 0K
描述: IC CTRLR BUCK POLYPHASE 36-SSOP
标准包装: 2,000
应用: 控制器,Intel 移动式 VID
输入电压: 4 V ~ 36 V
输出数: 1
输出电压: 0.6 V ~ 1.75 V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 36-SSOP(0.209",5.30mm 宽)
供应商设备封装: 36-SSOP
包装: 带卷 (TR)
LTC3730
APPLICATIO S I FOR ATIO
drain-to-gate accumulation capacitance and the gate-to-
source capacitance. The Miller charge (the increase in
coulombs on the horizontal axis from a to b while the curve
is flat) is specified for a given V DS drain voltage, but can be
adjusted for different V DS voltages by multiplying by the
ratio of the application V DS to the curve specified V DS
values. A way to estimate the C MILLER term is to take the
change in gate charge from points a and b on a manufac-
turers data sheet and divide by the stated V DS voltage
specified.C MILLER isthemostimportantselectioncriteria
for determining the transition loss term in the top MOSFET
but is not directly specified on MOSFET data sheets. C RSS
and C OS are specified sometimes but definitions of these
parameters are not included.
where N is the number of output stages, δ is the tempera-
ture dependency of R DS(ON) , R DR is the effective top driver
resistance (approximately 2 ? at V GS = V MILLER ), V IN is the
drain potential and the change in drain potential in the
particular application. V TH(IL) is the data sheet specified
typical gate threshold voltage specified in the power
MOSFET data sheet at the specified drain current. C MILLER
is the calculated capacitance using the gate charge curve
from the MOSFET data sheet and the technique described
above.
Both MOSFETs have I 2 R losses while the topside N-channel
equation includes an additional term for transition losses,
which peak at the highest input voltage. For V IN < 12V, the
V GS
MILLER EFFECT
a
b
Q IN
C MILLER = (Q B – Q A )/V DS
Figure 5
V
+
V GS
V IN
+ V DS
3730 F05
high current efficiency generally improves with larger
MOSFETs, while for V IN > 12V, the transition losses
rapidly increase to the point that the use of a higher
R DS(ON) device with lower C MILLER actually provides higher
efficiency. The synchronous MOSFET losses are greatest
at high input voltage when the top switch duty factor is low
or during a short circuit when the synchronous switch is
on close to 100% of the period.
Main Switch Duty Cycle =
Synchronous Switch Duty Cycle = ? IN OUT ?
?
? I
( )
P MAIN = OUT ? MAX ? 1 + δ R DS ( ON ) +
When the controller is operating in continuous mode the
duty cycles for the top and bottom MOSFETs are given by:
V OUT
V IN
? V – V ?
? V IN ?
The power dissipation for the main and synchronous
MOSFETs at maximum output current are given by:
2
V
V IN ? N ?
The term (1 + δ ) is generally given for a MOSFET in the
form of a normalized R DS(ON) vs temperature curve, but
δ = 0.005/ ° C can be used as an approximation for low
voltage MOSFETs.
The Schottky diodes, (D1 to D3 in Figure 1) conduct during
the dead time between the conduction of the two large
power MOSFETs. This prevents the body diode of the
bottom MOSFET from turning on, storing charge during
the dead time and requiring a reverse recovery period
which could cost as much as several percent in efficiency.
A 2A to 8A Schottky is generally a good compromise for
both regions of operation due to the relatively small
average current. Larger diodes result in additional transi-
tion loss due to their larger junction capacitance.
( R DR )( C MILLER ) ?
2 I MAX
? ( )
V IN – V OUT ? I MAX ?
( )
? ? 1 + δ R DS ( ON )
P SYNC =
14
V IN
2 N
? ?
? 1 1 ?
? + f
? V CC – V TH ( IL ) V TH ( IL ) ?
V IN ? N ?
2
C IN and C OUT Selection
In continuous mode, the source current of each top
N-channel MOSFET is a square wave of duty cycle V OUT /V IN .
A low ESR input capacitor sized for the maximum RMS
current must be used. The details of a close form equation
can be found in Application Note 77. Figure 6 shows the
input capacitor ripple current for different phase configu-
3730fa
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