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| 型号： | LTC3850IGN-2#TRPBF |
| 厂商： | Linear Technology |
| 文件页数： | 21/36页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM CM 28-SSOP |
| 产品培训模块： | LTC3850 Dual Output DC/DC Switching Regulator Controller |
| 标准包装： | 2,500 |
| 系列： | PolyPhase® |
| PWM 型： | 电流模式 |
| 输出数： | 2 |
| 频率 - 最大： | 860kHz |
| 占空比： | 97.2% |
| 电源电压： | 4 V ~ 30 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 28-SSOP（0.154"，3.90mm 宽） |
| 包装： | 带卷 (TR) |
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LTC3850-2
APPLICATIONS INFORMATION
both controllers are operating due to the reduced overlap of
current pulses required through the input capacitor’s ESR.
V OUT
This is why the input capacitor’s requirement calculated
1/2 LTC3850-2
R B
C FF
Δ V OUT ≈ I RIPPLE ? ESR +
abovefortheworst-casecontrollerisadequateforthedual
controller design. Also, the input protection fuse resistance,
battery resistance, and PC board trace resistance losses
are also reduced due to the reduced peak currents in a 2-
phase system. The overall bene?t of a multiphase design
will only be fully realized when the source impedance of the
power supply/battery is included in the ef?ciency testing.
The sources of the top MOSFETs should be placed within
1cm of each other and share a common C IN (s). Separating
the sources and C IN may produce undesirable voltage and
current resonances at V IN .
A small (0.1μF to 1μF) bypass capacitor between the chip
V IN pin and ground, placed close to the LTC3850-2, is also
suggested. A 2.2Ω – 10Ω resistor placed between C IN
(C1) and the V IN pin provides further isolation between
the two channels.
The selection of C OUT is driven by the effective series
resistance (ESR). Typically, once the ESR requirement
is satis?ed, the capacitance is adequate for ?ltering. The
output ripple (ΔV OUT ) is approximated by:
? 1 ?
?
? 8fC OUT ?
where f is the operating frequency, C OUT is the output
V FB
R A
38502 F09
Figure 9. Setting Output Voltage
To improve the frequency response, a feed-forward ca-
pacitor, C FF , may be used. Great care should be taken to
route the V FB line away from noise sources, such as the
inductor or the SW line.
Fault Conditions: Current Limit and Current Foldback
The LTC3850-2 includes current foldback to help limit
load current when the output is shorted to ground. If the
output falls below 50% of its nominal output level, then
the maximum sense voltage is progressively lowered from
its maximum programmed value to one-third of the maxi-
mum value. Foldback current limiting is disabled during
the soft-start or tracking up. Under short-circuit condi-
tions with very low duty cycles, the LTC3850-2 will begin
cycle skipping in order to limit the short-circuit current.
In this situation the bottom MOSFET will be dissipating
most of the power but less than in normal operation. The
short-circuit ripple current is determined by the minimum
on-time t ON(MIN) of the LTC3850-2 (≈ 90ns), the input
voltage and inductor value:
capacitance and I RIPPLE is the ripple current in the induc-
tor. The output ripple is highest at maximum input voltage
since I RIPPLE increases with input voltage.
Δ I L(SC) = t ON(MIN) ?
V IN
L
The resulting short-circuit current is:
– Δ I L(SC)
Setting Output Voltage
The LTC3850-2 output voltages are each set by an exter-
nal feedback resistive divider carefully placed across the
I SC =
1/3 V SENSE(MAX)
R SENSE
1
2
V OUT = 0.8V ? ? 1 + B ?
output,asshowninFigure9.Theregulatedoutputvoltage
is determined by:
? R ?
? R A ?
Phase-Locked Loop and Frequency Synchronization
The LTC3850-2 has a phase-locked loop (PLL) comprised of
an internal voltage-controlled oscillator (V CO ) and a phase
detector. This allows the turn-on of the top MOSFET of
controller 1 to be locked to the rising edge of an external
clock signal applied to the MODE/PLLIN pin. The turn-on
38502f
21
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