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| 型号： | LTC3850IGN-2#TRPBF |
| 厂商： | Linear Technology |
| 文件页数： | 22/36页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM CM 28-SSOP |
| 产品培训模块： | LTC3850 Dual Output DC/DC Switching Regulator Controller |
| 标准包装： | 2,500 |
| 系列： | PolyPhase® |
| PWM 型： | 电流模式 |
| 输出数： | 2 |
| 频率 - 最大： | 860kHz |
| 占空比： | 97.2% |
| 电源电压： | 4 V ~ 30 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 28-SSOP（0.154"，3.90mm 宽） |
| 包装： | 带卷 (TR) |
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LTC3850-2
APPLICATIONS INFORMATION
of controller 2’s top MOSFET is thus 180 degrees out-
of-phase with the external clock. The phase detector is
an edge sensitive digital type that provides zero degrees
phase shift between the external and internal oscillators.
This type of phase detector does not exhibit false lock to
harmonics of the external clock.
The output of the phase detector is a pair of complemen-
tary current sources that charge or discharge the external
?lter network connected to the FREQ/PLLFLTR pin. The
relationship between the voltage on the FREQ/PLLFLTR
pin and operating frequency is shown in Figure 10 and
speci?ed in the Electrical Characteristics table. Note that the
LTC3850-2 can only be synchronized to an external clock
whose frequency is within range of the LTC3850-2’s internal
V CO . This is guaranteed to be between 250kHz and 780kHz.
A simpli?ed block diagram is shown in Figure 11.
900
800
700
600
500
400
300
If no clock is applied to MODE/PLLIN pin, the FREQ/
PLLFLTR pin will be high impedance.
If the external clock frequency is greater than the internal
oscillator’s frequency, f OSC , then current is sourced con-
tinuously from the phase detector output, pulling up the
FREQ/PLLFLTR pin. When the external clock frequency is
less than f OSC , current is sunk continuously, pulling down
the FREQ/PLLFLTR pin. If the external and internal frequen-
cies are the same but exhibit a phase difference, the current
sources turn on for an amount of time corresponding to the
phase difference. The voltage on the FREQ/PLLFLTR pin is
adjusted until the phase and frequency of the internal and
external oscillators are identical. At the stable operating
point, the phase detector output is high impedance and
the ?lter capacitor C LP holds the voltage.
The loop ?lter components, C LP and R LP , smooth out the
current pulses from the phase detector and provide a stable
input to the voltage-controlled oscillator. The ?lter compo-
nents C LP and R LP determine how fast the loop acquires
lock. Typically R LP = 10k and C LP is 2200pF to 0.01μF.
Typically, the external clock (on MODE/PLLIN pin) input high
threshold is 1.6V, while the input low thres-hold is 1V.
Minimum On-Time Considerations
200
100
0
0
0.5 1 1.5 2
FREQ/PLLFLTR PIN VOLTAGE (V)
2.5
38502 F10
Minimum on-time t ON(MIN) is the smallest time duration that
the LTC3850-2 is capable of turning on the top MOSFET.
It is determined by internal timing delays and the gate
charge required to turn on the top MOSFET. Low duty
Figure 10. Relationship Between Oscillator
Frequency and Voltage at the FREQ/PLLFLTR Pin
cycle applications may approach this minimum on-time
limit and care should be taken to ensure that
2.4V
R LP
t ON(MIN) <
V OUT
V IN (f)
C LP
EXTERNAL
OSCILLATOR
MODE/
PLLIN
DIGITAL
PHASE/
FREQUENCY
DETECTOR
FREQ/
PLLFLTR
VCO
If the duty cycle falls below what can be accommodated
by the minimum on-time, the controller will begin to skip
cycles. The output voltage will continue to be regulated,
but the ripple voltage and current will increase.
The minimum on-time for the LTC3850-2 is approximately
90ns, with reasonably good PCB layout, minimum 30%
inductor current ripple and at least 10mV – 15mV ripple
38502 F11
Figure 11. Phase-Locked Loop Block Diagram
38502f
22
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