参数资料
型号: LTC3856EUH#PBF
厂商: Linear Technology
文件页数: 22/40页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM CM 32WFQFN
标准包装: 73
系列: PolyPhase®
PWM 型: 电流模式
输出数: 1
频率 - 最大: 850kHz
占空比: 94%
电源电压: 4.5 V ~ 38 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 125°C
封装/外壳: 32-WFQFN 裸露焊盘
包装: 管件
LTC3856
APPLICATIONS INFORMATION
V OUT
V IN
Synchronous Switc h Duty Cycle = ? IN
? I
?
V
P MAIN = OUT ? MAX ? ( 1 + δ ) R DS ( ON ) +
( V IN ) 2 ? ? MAX N ? ? ( R DR )( C MILLER ) ?
V
+ V
? ?
+
?
? ? f
V – V OUT ? I MAX ?
P SYNC = IN ( 1 + δ ) R DS ( ON )
Thepeak-to-peakMOSFETgatedrivelevelsaresetbythe
voltage, V CC , requiring the use of logic-level threshold
MOSFETs in most applications. Pay close attention to the
BV DSS specification for the MOSFETs as well; many of the
logic-level MOSFETs are limited to 30V or less. Selection
criteria for the power MOSFETs include the on-resistance,
R DS(ON) , input capacitance, input voltage and maximum
output current. MOSFET input capacitance is a combination
of several components but can be taken from the typical
gate charge curve included on most data sheets (Figure 9).
The curve is generated by forcing a constant input current
into the gate of a common source, current source loaded
stage, then plotting the gate voltage versus time.
V IN
MILLER EFFECT
V GS
a b
+ DS
Q IN V GS
C MILLER = (Q B – Q A )/V DS –
3856 F09
Figure 9. Gate Charge Characteristic
The initial slope is the effect of the gate-to-source and
the gate-to-drain capacitance. The flat portion of the
curve is the result of the Miller multiplication effect of the
drain-to-gate capacitance as the drain drops the voltage
across the current source load. The upper sloping line is
due to the drain-to-gate accumulation capacitance and
the gate-to-source capacitance. The Miller charge (the
increase in coulombs on the horizontal axis from a to b
while the curve is flat) is specified for a given V DS drain
voltage, but can be adjusted for different V DS voltages by
multiplying the ratio of the application V DS to the curve
specified V DS values. A way to estimate the C MILLER
term is to take the change in gate charge from points
a and b on a manufacturer’s data sheet and divide by
the stated V DS voltage specified. C MILLER is the most
important selection criteria for determining the transition
loss term in the top MOSFET but is not directly specified
on MOSFET data sheets. C RSS and C OS are specified
sometimes but definitions of these parameters are not
included. When the controller is operating in continuous
mode, the duty cycles for the top and bottom MOSFETs
are given by:
Main Switch Duty Cycle =
? V – V OUT ?
?
? V IN ?
The power dissipation for the main and synchronous
MOSFETs at maximum output current are given by:
2
V IN ? N ?
? I ?
2
1 1
? ?
? V CC – V TH ( IL ) V TH ( IL ) ?
2
? ?
V IN ? N ?
where N is the number of output stages, δ is the tem-
perature dependency of R DS(ON) , R DR is the effective top
driver resistance (approximately 2Ω at V GS = V MILLER ),
V IN is the drain potential and the change in drain poten-
tial in the particular application. V TH(IL) is the data sheet
specified typical gate threshold voltage specified in the
power MOSFET data sheet at the specified drain current.
C MILLER is the calculated capacitance using the gate charge
curve from the MOSFET data sheet and the technique just
described.
Both MOSFETs have I 2 R losses while the topside N-channel
equation includes an additional term for transition losses,
which peak at the highest input voltage. For V IN < 20V,
the high current efficiency generally improves with larger
MOSFETs, while for V IN > 20V, the transition losses rapidly
increase to the point that the use of a higher R DS(ON) device
with lower C MILLER actually provides higher efficiency. The
synchronous MOSFET losses are greatest at high input
voltage when the top switch duty factor is low, or during
a short-circuit when the synchronous switch is on close
to 100% of the period.
3856f
  
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