参数资料
型号: LTC3900MPS8
厂商: LINEAR TECHNOLOGY CORP
元件分类: 稳压器
英文描述: SWITCHING REGULATOR, PDSO8
封装: PLASTIC, SOP-8
文件页数: 19/20页
文件大小: 277K
代理商: LTC3900MPS8
LTC3900
8
3900fb
applicaTions inForMaTion
ThetimercircuitandcurrentsensecomparatorinLTC3900
are used to prevent reverse current buildup in the output
inductor.
Timer
Figure 3 shows the LTC3900 timer internal and external
circuits. The timer operates by using an external R-C
charging network to program the time-out period. On
every negative transition at the SYNC input, the chip
generates a 200ns pulse to reset the timer cap. If the
SYNC signal is missing or incorrect, allowing the timer
cap voltage to go high, it shuts off both drivers once the
voltage reaches the time-out threshold. Figure 4 shows
the timer waveforms.
A typical forward converter cycle always turns on Q3
and Q4 alternately and the SYNC input should alternate
between positive and negative pulses. The LTC3900 timer
also includes sequential logic to monitor the SYNC input
sequence. If after one negative pulse, the SYNC compara-
tor receives another negative pulse, the LTC3900 will not
reset the timer cap. If no positive SYNC pulse appears,
both drivers are shut off once the timer times out. Once
positive pulses reappear the timer resets and the drivers
start switching again. This is to protect the external com-
ponents in situations where only negative SYNC pulse is
present and FG output remains high. Figure 5 shows the
timer waveforms with incorrect SYNC pulses.
The LTC3900 has two separate SYNC comparators (S+ and
SintheBlockDiagram)todetectthepositiveandnegative
pulses. The threshold voltages of both comparators are
Figure 3. Timer Circuit
ZTMR
RTMR
CTMR
7
3900 F03
TMR
4
R1
R2
VCC
TIMEOUT
TIMER
RESET
designed to be of the same magnitude (1.4V typical) but
opposite in polarity. In some situations, for example dur-
ing power up or power down, the SYNC pulse magnitude
may be low, slightly higher or lower than the threshold of
the comparators. This can cause only one of the SYNC
comparators to trip. This also appears as incorrect SYNC
pulse and the timer will not reset.
The timeout period is determined by the external RTMR
and CTMR values and is independent of the VCC voltage.
This is achieved by making the timeout threshold a ratio
of VCC. The ratio is 0.2x, set internally by R1 and R2 (see
Figure 3). The timeout period should be programmed to
be around one period of the primary switching frequency
using the following formula:
TIMEOUT = 0.2 RTMR CTMR + 0.27E-6
To reduce error in the timeout setting due to the discharge
time, select CTMR between 100pF and 1000pF. Start with a
CTMRaround 470pF and then calculate the required RTMR.
CTMRshouldbeplacedascloseaspossibletotheLTC3900
with minimum PCB trace between CTMR, the TIMER pin
and GND. This is to reduce any ringing caused by the PCB
trace inductance when CTMR discharges. This ringing may
introduce error to the timeout setting.
The timer input also includes a current sinking clamp
circuit (ZTMR in Figure 3) that clamps this pin to about
0.5 VCC if there is missing SYNC/timer reset pulse. This
clamp circuit prevents the timer cap from getting fully
charged up to the rail, which results in a longer discharge
SYNC
FG
CG
TIMER RESET
(INTERNAL)
TIMER
SG
TIMEOUT
THRESHOLD
LAST
PULSE
3900 F04
Figure 4. Timer Waveforms
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