参数资料
型号: LTC4252A-2IMS
厂商: Linear Technology
文件页数: 12/36页
文件大小: 328K
描述: IC CTRLR HOTSWAP NEG VOLT 10MSOP
标准包装: 50
类型: 热交换控制器
应用: 通用
内部开关:
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 10-TFSOP,10-MSOP(0.118",3.00mm 宽)
供应商设备封装: 10-MSOP
包装: 管件
LTC4252-1/LTC4252-2
LTC4252A-1/LTC4252A-2
12
425212fe
For more information www.linear.com/LTC4252-1
operaTion
Hot Circuit Insertion
When circuit boards are inserted into a live backplane, the
supply bypass capacitors can draw huge transient currents
from the power bus as they charge. The flow of current
damages the connector pins and glitches the power bus,
causing other boards in the system to reset. The LTC4252
is designed to turn on a circuit board supply in a controlled
manner, allowing insertion or removal without glitches or
connector damage.
Initial Start-Up
The LTC4252 resides on a removable circuit board and
controls the path between the connector and load or power
conversion circuitry with an external MOSFET switch (see
Figure 1). Both inrush control and short-circuit protection
are provided by the MOSFET .
A detailed schematic for the LTC4252A is shown in Figure?.
48V and 48RTN receive power through the longest con-
nector pins and are the first to connect when the board is
inserted. The GATE pin holds the MOSFET off during this
time. UV and OV determine whether or not the MOSFET
should be turned on based upon internal high accuracy
thresholds and an external divider. UV and OV do double
duty by also monitoring whether or not the connector is
seated. The top of the divider detects 48RTN by way of
a short connector pin that is the last to mate during the
insertion sequence.
Interlock Conditions
A start-up sequence commences once these interlock
conditions are met.
1. The input voltage V
IN
 exceeds V
LKO
 (UVLO).
2. The voltage at UV > V
UVHI
.
3. The voltage at OV < V
OVLO
.
4. The (SENSE  V
EE
) voltage is < 50mV (V
CB
).
5. The voltage at SS is < 0.2V (20 " V
OS
).
6. The voltage on the TIMER capacitor (C
T
) is < 1V (V
TMRL
).
7. The voltage at GATE is < 0.5V (V
GATEL
).
The first three conditions are continuously monitored and
the latter four are checked prior to initial timing or GATE
ramp-up. Upon exiting an OV condition, the TIMER pin
voltage requirement is inhibited. Details are described in
the Applications Information, Timing Waveforms section.
TIMER begins the start-up sequence by sourcing 5.8礎
into C
T
. If V
IN
, UV or OV falls out of range, the start-up
cycle stops and TIMER discharges C
T
 to less than 1V , then
waits until the aforementioned conditions are once again
met. If C
T
 successfully charges to 4V , TIMER pulls low
and both SS and GATE pins are released. GATE sources
58礎 (I
GATE
), charging the MOSFET gate and associated
capacitance. The SS voltage ramp limits V
SENSE
 to control
the inrush current. PWRGD pulls active low when GATE is
within 2.8V of V
IN
 and DRAIN is lower than V
DRNL
.
4252-1/2 F01
LTC4252
C
LOAD
ISOLATED
DC/DC
CONVERTER
MODULE
LOW
VOLTAGE
CIRCUITRY
+
+


PLUG-IN BOARD
BACKPLANE
48RTN
48V
LONG
LONG
+
Figure 1. Basic LTC4252 Hot Swap Topology
Figure 2. 48V, 2.5A Hot Swap Controller
425212 F02
48RTN
48V
UV
OV
TIMER
V
EE
V
IN
SENSE GATE
SS
DRAIN
LTC4252A-1
R1
392k
1%
D
IN
+
DDZ13B**
R2
30.1k
1%
R
D
1M
C
T
0.68礔
C
SS
68nF
C
C
10nF
R
S
0.02
Q1
IRF530S
R
C
10
R
IN
3 ?1.8k IN SERIES
1/4W EACH
C1
10nF
C
IN
1礔
C
LOAD
100礔
LONG
LONG
SHORT
+
**DIODES, INC
 
RECOMMENDED FOR HARSH ENVIRONMENTS
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