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参数资料
| 型号： | LTC4252A-2IMS |
| 厂商： | Linear Technology |
| 文件页数： | 22/36页 |
| 文件大小： | 328K |
| 描述： | IC CTRLR HOTSWAP NEG VOLT 10MSOP |
| 标准包装： | 50 |
| 类型： | 热交换控制器 |
| 应用： | 通用 |
| 内部开关： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 10-TFSOP，10-MSOP（0.118"，3.00mm 宽） |
| 供应商设备封装： | 10-MSOP |
| 包装： | 管件 |
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LTC4252-1/LTC4252-2
LTC4252A-1/LTC4252A-2
22
425212fe
For more information www.linear.com/LTC4252-1
applicaTions inForMaTion
At time point 8, the load current falls and the SENSE voltage
drops below V
ACL
(t). The analog current limit loop shuts
off and the GATE pin ramps further. At time point 9, the
SENSE voltage drops below V
CB
, the fault TIMER cycle
ends, followed by a 5.8礎 discharge cycle (cool off). The
duration between time points 7 and 9 must be shorter than
one circuit breaker delay to avoid a fault time out during
GATE ramp-up. When GATE ramps past the V
GATEH
thresh-
old at time point 10, PWRGD pulls low. At time point?1,
GATE reaches its maximum voltage as determined by V
IN
.
Live Insertion with Short Pin Control of UV/OV
In the example shown in Figure 10, power is delivered
through long connector pins whereas the UV/OV divider
makes contact through a short pin. This ensures the power
connections are firmly established before the LTC4252 is
activated. At time point 1, the power pins make contact
and V
IN
ramps through V
LKO
. At time point 2, the UV/OV
divider makes contact and its voltage exceeds V
UVHI
. In
addition, the internal logic checks for OV < V
OVHI
, GATE
< V
GATEL
,
SENSE < V
CB
, SS < 20 " V
OS
and TIMER <
V
TMRL
. If all conditions are met, an initial timing cycle
starts and the TIMER capacitor is charged by a 5.8礎
current source pull-up. At time point 3, TIMER reaches the
V
TMRH
threshold and the initial timing cycle terminates.
The TIMER capacitor is quickly discharged. At time point
4, the V
TMRL
threshold is reached and the conditions of
GATE < V
GATEL
, SENSE < V
CB
and SS < 20 " V
OS
must be
GND V
EE
OR
(48RTN) (48V)
UV/OV
V
IN
TIMER
GATE
V
LKO
SENSE
V
IN
CLEARS V
LKO
, CHECK UV > V
UVHI
, OV < V
OVLO
, GATE < V
GATEL
, SENSE < V
CB
, SS < 20 " V
OS
AND TIMER < V
TMRL
V
OUT
1 2
3 4 56 7 8
V
ACL
V
CB
9
TIMER CLEARS V
TMRL
, CHECK GATE < V
GATEL
, SENSE < V
CB
AND SS < 20 " V
OS
SS
DRAIN
PWRGD
230礎 + 8 " I
DRN
5.8礎
20 " V
OS
58礎
1011
V
IN
V
GATEH
V
DRNL
V
DRNCL
20 " (V
CB
+ V
OS
)
20 " (V
ACL
+ V
OS
)
V
GATEL
V
TMRL
V
TMRH
5.8礎
5.8礎
58礎
425212 F09
GATE
START-UP
INITIAL TIMING
Figure 9. System Power-Up Timing (All Waveforms Are Referenced to V
EE
)
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相关代理商/技术参数 |
参数描述 |
|---|---|
| LTC4252A-2IMS#PBF | 功能描述:IC CNTRLR HOTSWAP NEGVOLT 10MSOP RoHS:是 类别:集成电路 (IC) >> PMIC - 热交换 系列:- 产品培训模块:Obsolescence Mitigation Program 标准包装:100 系列:- 类型:热插拔开关 应用:通用 内部开关:是 电流限制:可调 电源电压:9 V ~ 13.2 V 工作温度:-40°C ~ 150°C 安装类型:表面贴装 封装/外壳:10-WFDFN 裸露焊盘 供应商设备封装:10-TDFN-EP（3x3） 包装:管件 |
| LTC4252A-2IMS#TR | 功能描述:IC CTRLR HOTSWAP NEG VOLT 10MSOP RoHS:否 类别:集成电路 (IC) >> PMIC - 热交换 系列:- 产品培训模块:Obsolescence Mitigation Program 标准包装:100 系列:- 类型:热插拔开关 应用:通用 内部开关:是 电流限制:可调 电源电压:9 V ~ 13.2 V 工作温度:-40°C ~ 150°C 安装类型:表面贴装 封装/外壳:10-WFDFN 裸露焊盘 供应商设备封装:10-TDFN-EP（3x3） 包装:管件 |
| LTC4252A-2IMS#TRPBF | 功能描述:IC CNTRLR HOTSWAP NEGVOLT 10MSOP RoHS:是 类别:集成电路 (IC) >> PMIC - 热交换 系列:- 产品培训模块:Obsolescence Mitigation Program 标准包装:100 系列:- 类型:热插拔开关 应用:通用 内部开关:是 电流限制:可调 电源电压:9 V ~ 13.2 V 工作温度:-40°C ~ 150°C 安装类型:表面贴装 封装/外壳:10-WFDFN 裸露焊盘 供应商设备封装:10-TDFN-EP（3x3） 包装:管件 |
| LTC4252A-2IMSPBF | 制造商:LINER 制造商全称:Linear Technology 功能描述:Negative Voltage Hot Swap Controllers |
| LTC4252A-2IMSTR | 制造商:LINER 制造商全称:Linear Technology 功能描述:Negative Voltage Hot Swap Controllers |
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