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参数资料
| 型号： | LXT384LE |
| 元件分类： | 通信、网络模块及开发工具 |
| 英文描述： | Telecomm/Datacomm |
| 中文描述： | 电信/数据通信 |
| 文件页数： | 18/80页 |
| 文件大小： | 1112K |
| 代理商： | LXT384LE |
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LXT384
—
Octal T1/E1/J1 Transceiver
18
Datasheet
69
69
70
70
P12
P12
P13
P13
RNEG3
BPV3
RPOS3
RDATA3
DO
DO
DO
DO
Receive Negative Data Output.
Bipolar Violation Detect Output.
Receive Positive Data Output.
Receive Data Output.
71
P14
RCLK3
DO
Receive Clock Output.
72
72
73
73
N12
N12
N13
N13
TNEG3
UBS3
TPOS3
TDATA3
DI
DI
DI
DI
Transmit Negative Data Input.
Unipolar/Bipolar Select Input.
Transmit Positive Data Input.
Transmit Data Input.
74
N14
TCLK3
DI
Transmit Clock Input.
75
K12
LOS2
DO
Loss of Signal Output.
76
76
77
77
M12
M12
M13
M13
RNEG2
BPV2
RPOS2
RDATA2
DO
DO
DO
DO
Receive Negative Data Output.
Bipolar Violation Detect Output.
Receive Positive Data Output.
Receive Data Output.
78
M14
RCLK2
DO
Receive Clock Output.
79
79
80
80
L12
L12
L13
L13
TNEG2
UBS2
TPOS2
TDATA2
DI
DI
DI
DI
Transmit Negative Data Input.
Unipolar/Bipolar Select Input.
Transmit Positive Data Input.
Transmit Data Input.
81
L14
TCLK2
DI
Transmit Clock Input.
82
K13
INT
OD
Interrupt.
This active Low, maskable, open drain output requires an
external 10k pull up resistor. If the corresponding interrupt enable bit is
enabled, INT goes Low to flag the host when the
LXT384
changes state
(see details in the interrupt handling section). The microprocessor INT
input should be set to level triggering.
83
83
83
K14
K14
K14
ACK
RDY
SDO
DO
DO
DO
Data Transfer Acknowledge Output (Motorola Mode).
Ready Output (Intel mode).
Serial Data Output
(Serial Mode).
Motorola Mode
A Low signal during a data bus read operation indicates that the
information is valid. A Low signal during a write operation acknowledges
that a data transfer into the addressed register has been accepted
(acknowledge signal).Wait states only occur if a write cycle immediately
follows a previous read or write cycle (e.g. read modify write).
Intel Mode
A High signal acknowledges that a register access operation has been
completed. (Ready Signal) A Low signal on this pin signals that a data
transfer operation is in progress. The pin goes tristate after completion
of a bus cycle.
Serial Mode
If CLKE is High, SDO is valid on the rising edge of SCLK. If CLKE is
Low, SDO is valid on the falling edge of SCLK. This pin goes into High Z
state during a serial port write access.
Table 1. LXT384 Pin Description (Sheet 8 of 12)
Pin #
QFP
Ball #
PBGA
Symbol
I/O
1
Description
1. DI: Digital Input; DO: Digital Output; DI/O: Digital Bidirectional Port; AI: Analog Input; AO: Analog Output
S: Power Supply; N.C.: Not Connected.
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相关代理商/技术参数 |
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|---|---|
| LXT386 | 制造商:INTEL 制造商全称:Intel Corporation 功能描述:QUAD T1/E1/J1 Transceiver |
| LXT386BE | 制造商:未知厂家 制造商全称:未知厂家 功能描述:PCM TRANSCEIVER|QUAD|CEPT PCM-30/E-1|CMOS|BGA|160PIN|PLASTIC |
| LXT386LE | 制造商:LEVEL1 功能描述: |
| LXT388LE | 制造商:未知厂家 制造商全称:未知厂家 功能描述:PCM TRANSCEIVER|DUAL|CEPT PCM-30/E-1|CMOS|QFP|100PIN|PLASTIC |
| LXT400 | 制造商:LVL1 制造商全称:LVL1 功能描述:All Rate Extended Range Switched 56/DDS Transceiver |
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