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| 型号： | LXT384LE |
| 元件分类： | 通信、网络模块及开发工具 |
| 英文描述： | Telecomm/Datacomm |
| 中文描述： | 电信/数据通信 |
| 文件页数： | 37/80页 |
| 文件大小： | 1112K |
| 代理商： | LXT384LE |
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Octal T1/E1/J1 Transceiver
—
LXT384
Datasheet
37
2.13.2
Interrupt Enable
The LXT384 provides a latched interrupt output (INT). An interrupt occurs any time there is a
transition on any enabled bit in the status register. Registers 06H, 07H and 14H are the LOS, DFM
and AIS interrupt enable registers (respectively). Writing a logic
“
1
”
into the mask register will
enable the respective bit in the respective Interrupt status register to generate an interrupt. The
power-on default value is all zeroes. The setting of the interrupt enable bit does not affect the
operation of the status registers.
Registers 08H, 09H and 15H are the LOS, DFM and AIS (respectively) interrupt status registers.
When there is a transition on any enabled bit in a status register, the associated bit of the interrupt
status register is set and an interrupt is generated (if one is not already pending). When an interrupt
occurs, the INT pin is asserted Low. The output stage of the INT pin consists only of a pull-down
device; an external pull-up resistor of approximately 10k ohm is required to support wired-OR
operation.
2.13.3
Interrupt Clear
When an interrupt occurs, the interrupt service routine (ISR) should read the
interrupt status
registers
(08H, 09H and 15H) to identify the interrupt source. Reading the Interrupt Status register
clears the "sticky" bit set by the interrupt. Automatically clearing the register prepares it for the
next interrupt.
The ISR should then read the corresponding
status monitor register
to obtain the current status of
the device. Note: there are three status monitor registers: the LOS (04H), the DFM (05H) and the
AIS (013H). Reading either status monitors register will clear its corresponding interrupts on the
rising edge of the read or data strobe. When all pending interrupts are cleared, the INT pin goes
High.
2.14
Serial Host Mode
The LXT384 operates in Serial Host Mode when the MODE pin is tied to VCCIO
÷
2.
Figure 14
shows the SIO data structure. The registers are accessible through a 16 bit word: an 8bit Command/
Address byte (bits R/W and A1-A7) and a subsequent 8bit data byte (bits D0-7). Bit R/W
determines whether a read or a write operation occurs. Bits A5-0 in the Command/Address byte
address specific registers (the address decoder ignores bits A7-6). The data byte depends on both
the value of bit R/W and the address of the register as set in the Command/Address byte.
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