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参数资料
| 型号： | LXT6155LE |
| 元件分类： | 通信、网络模块及开发工具 |
| 英文描述： | Telecomm/Datacomm |
| 中文描述： | 电信/数据通信 |
| 文件页数： | 21/48页 |
| 文件大小： | 1105K |
| 代理商： | LXT6155LE |
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Intel
LXT6155 155 Mbps SDH/SONET/ATM Transceiver
Datasheet
21
2.5.1.3
Line Interface Selection (MODE Pin)
The MODE pin sets one of the two line interfaces, as described in
Table 5
.
2.5.1.4
Parallel/Serial Mode Selection (SP pin)
In Hardware Mode, HWSEL = Low, the Intel
LXT6155 can be set to operate in serial or parallel
data mode, depending on how the Serial/Parallel SP pin is set.
Setting the SP pin = High sets the Intel
LXT6155 to an 8-bit parallel mode. Parallel pins
TPID<7:0>, TPICLK, RPOD<7:0>, ROFP, RPOCLK, LOCK and LOS are be used. Serial pins
TPOS, TNEG, TSICLKP, TSICLKN, RPOS, RNEG, RSOCLKP, RSOCLKN are unused and
should be left open.
Setting the SP pin = Low sets the Intel
LXT6155 to serial mode. Pins TPOS, TNEG, TSICLKP,
TSICLKN, RPOS, RNEG, RSOCLKP, RSOCLKN, LOCK and LOS are used. Pins TPID<7:0>,
TPICLK, RPOD<7:0> and RPOCLK are unused and should be left open.
2.5.1.5
Tx Amplitude Trim
In Hardware, serial, coax mode, the line driver output amplitude can be controlled via pins 16 to
20. Setting TXTRIMENA (pin #20) high enables the trim capability. The trim rage is -21% to
+24% in 3% steps controlled by TXTRIM0-TXTRIM3. The minimum amplitude is at 0000 and the
maximum amplitude is at 1111. This is the same control range as in SW mode.
2.5.2
Software Mode
When HWSEL = High, the Intel
LXT6155 operates in Software Mode. Control is through an
external serial
μ
P interface.
Figure 9
shows the pins used in Software Mode. The Intel
LXT6155
uses four pins for the industry standard Serial Control Interface (SCP) bus: SCLK, CS, SDI and
SDO. SCLK is the serial input control clock pin. CS is the chip select input. SDI is the serial data
input pin, and SDO is the serial data output pin.
Figure 10
and
Figure 11
show the serial interface
data structure. A data transaction is initiated by a falling edge on the Chip Select pin CS. A High-
to-Low transition on CS is required for each access to the control registers. The first bit is a read/
write bit (R/W), followed by seven address bits (A<6:0>), and eight data bits (D<7:0>). Every data
transaction requires 16 SCLK cycles to complete. If R/W = High (Read), the Intel
LXT6155
outputs a data byte D<7:0> on the SDO pin. If R/W = Low (Write), the Intel
LXT6155 accepts a
data byte D<7:0> on the SDI pin, while tristating SDO pin.
It is recommended in SW mode operation, the registers are first initialized by writing a “0” to
register #11 bit #6 (reset).
Table 5. MODE Line Interface Settings
MODE
Description
Low
Sets LVPECL NRZ mode to interface to a fiber
optic module. CMI related blocks (e.g. input/output
buffers, equalizer) are disabled.
High
Sets CMI mode to interface to a transformer and a
75
coax cable. NRZ related input/output buffers
are disabled.
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