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参数资料
| 型号： | LXT6155LE |
| 元件分类： | 通信、网络模块及开发工具 |
| 英文描述： | Telecomm/Datacomm |
| 中文描述： | 电信/数据通信 |
| 文件页数： | 31/48页 |
| 文件大小： | 1105K |
| 代理商： | LXT6155LE |
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Intel
LXT6155 155 Mbps SDH/SONET/ATM Transceiver
Datasheet
31
.
.
3
0
frame_ena
Byte align enable: If used, this feature must be enabled during system
configuration prior to applying data to the receiver. If this is not
possible see the Intel
LXT6155
155 Mbps SDH/SONET/ATM
Transceiver Application Note
(Intel order number 249280) for further
details.
0 = byte align disabled
1 = byte align enabled
2
0
Not for customer use.
1
0
Not for customer use.
0
1
Not for customer use.
Table 21. Rx Digital 2, Register #13 (Address A<3:0>=11001)
Bit
Default
Mnemonic
Description
7
1
rx_dig_reset
Rx digital circuitry reset. This can be used to minimize power
comsumption when the device is disabled but not powered down. It
must be enabled when the device is active
0 = reset
1 = normal operation
6:3
0.0.0.0
cnffp
Frame pulse position. Refer to
Figure 5
for usage.
2:1
1.0
los_tran_assert
D-LOS transition density count for assertion:
00 = 128
01 = 512
10 = 3112
11 = 4096
A-LOS assertion integration period:
00 = 2048 bits
01 = 512 bits
10 = 128 bits
11 = 32 bits
0
1
los_tran_deass
ert
D-LOS transition density count for de-assertion:
0 = 4/32
1 = SONET compliant
1
A-LOS de-assertion integration period:
0 = 0 bits
1 = 128 bits
1. SONET compliant LOS de-assertion refers to Bellcore GR-253, pages 6-16 (section 6.2.1.1.1),
recommendation R6-54, LOS alarm is de-asserted (cleared) when two valid frame headers have been
received with no LOS events in the interval.
Table 22. Status Control, Register #14 (Address A<3:0>=1110)
Bit
Default
Mnemonic
Description
7:4
0.0.0.0
-
Unused
3:0
0.0.0.0
stat_cont
Status register (register #15) mux control (indirect addressing to
increase read space)
Table 20. Rx Digital 1, Register #12 (Address A<3:0>=1100) (Continued)
Bit
Default
Mnemonic
Description
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