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参数资料
| 型号： | LXT6155LE |
| 元件分类： | 通信、网络模块及开发工具 |
| 英文描述： | Telecomm/Datacomm |
| 中文描述： | 电信/数据通信 |
| 文件页数： | 22/48页 |
| 文件大小： | 1105K |
| 代理商： | LXT6155LE |
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Intel
LXT6155 155 Mbps SDH/SONET/ATM Transceiver
22
Datasheet
2.5.2.1
Serial Input Clock (SCLK)
This pin accepts a clock up to 4.096 MHz for data transactions between the Intel
LXT6155 and
the SCP bus. The Intel
LXT6155 clocks SDO data out on the falling edge, and clocks SDI data in
on the rising edge of SCLK (see
Figure 10
and
Figure 11
).
2.5.2.2
Chip Select Input (CS)
On the falling edge of CS, the Intel
LXT6155 starts data transactions. On the rising edge of CS,
the Intel
LXT6155 stops data transaction. The CS pin must be held Low for at least 16 SCLK
cycles to complete a full Read or Write data transaction. If CS is held Low less than 16 SCLK
cycles, then the data transaction is ignored. At the end of each Write/Read transaction, CS must
return High, between the 16th and 17th clock edges.
2.5.2.3
Serial Input Word (SDI)
Figure 11
shows the serial interface input data word structure. When the first input bit R/W = Low,
a Write operation is performed. The SCLK clocks data in on the SDI pin during the second 8 bits
D<7:0> of the Write operation. Data is clocked in on the rising edge of SCLK. During the entire 16
bit operation, SDO remains tristated. Refer to
Table 6
through
Table 23
for control register
descriptions.
2.5.2.4
Serial Output Word (SDO)
The serial output word structure is shown in
Figure 10
. When the first input bit R/W = High, a
Read operation is specified. SDO becomes active after A0 has been clocked in. The first bit out of
SDO changes the state of SDO from High-Z to a Low/High. SDO is clocked out on the falling edge
of SCLK.
Figure 9. Software Mode
LXT6155
HWSEL
CS
SDI
SCLK
VCC
Chip select in
Serial data in
Serial clock in
SDO
Serial data out
ADDR0, ADDR1
Device address settings
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