Intel
LXT6155 155 Mbps SDH/SONET/ATM Transceiver
Datasheet
37
Table 28. DC Electrical Characteristics
(Vcc = 3.0 V to 3.6 V; TA = -40
°
C to 85 °C)
Parameter
Sym
Min
Typ
1
Max
Unit
Test Conditions
High level input voltage (LVPECL)
Vih1
Vcc-1.03
Vcc-0.88
V
Low level input voltage (LVPECL)
Vil1
Vcc-1.81
Vcc-1.62
V
High level output voltage (LVPECL)
Voh1
Vcc-1.03
Vcc-0.95
Vcc-0.88
V
50
pulled
down to V
CC
-
2.0 V.
Low level output voltage (LVPECL)
Vol1
Vcc-1.81
Vcc-1.70
Vcc-1.62
V
High level input voltage (TTL)
Vih2
2.0
V
Low level input voltage (TTL)
Vil2
0.8
V
High level output voltage (TTL)
Voh2
2.4
V
I
OH
= 4 mA
Low level output voltage (TTL)
Vol2
0.4
V
I
OL
= 4 mA
Input leakage current, low (TTL)
Ill
10
μ
A
Input leakage current, high (TTL)
Ilh
10
μ
A
1. Typical values are at 25 C and 3.3 V. They are for design aid only; not guaranteed and not subject to
production testing.
Table 29. Transmit Timing Characteristics
(See
Figure 18
and
Figure 19
)
Parameter
Sym
Min
Typ
1
Max
Unit
Test Conditions
Transmit serial input clock frequency
155.52
MHz
Transmit serial input clock frequency error
-20
+20
ppm
Compliant with GR253
Transmit serial input clock duty cycle
45
55
%
Transmit serial input clock and data rise /
fall time
1.2
ns
20% - 80%
Transmit parallel input clock frequency
19.44
MHz
Transmit parallel input clock frequency
error
-20
+20
ppm
Transmit parallel input clock duty cycle
45
55
%
Transmit parallel input data & clock rise/
fall time
2
10
ns
TPICLK to TPID<0:7> hold time
Thtpid
3
ns
TPICLK to TPID<0:7> setup time
Tstpid
2
ns
TSICLKP(TSICLKN) to TPOS (TNEG)
setup time
Tstpos
1.25
ns
TSICLKP (TSICLKN) to TPOS (TNEG)
hold time
Thtpos
0.75
ns
1. Typical values are at 25 C and 3.3 V. They are for design aid only; not guaranteed and not subject to
production testing.
2. Not production tested, guaranteed by design and other correlation factors.