参数资料
型号: M1A3PE1500-FGG484
厂商: Microsemi SoC
文件页数: 140/162页
文件大小: 0K
描述: IC FPGA 1KB FLASH 1.5M 484-FBGA
标准包装: 40
系列: ProASIC3E
RAM 位总计: 276480
输入/输出数: 280
门数: 1500000
电源电压: 1.425 V ~ 1.575 V
安装类型: 表面贴装
工作温度: 0°C ~ 70°C
封装/外壳: 484-BGA
供应商设备封装: 484-FPBGA(23x23)
ProASIC3E Flash Family FPGAs
Revision 13
2-65
Timing Characteristics
VersaTile Specifications as a Sequential Module
The ProASIC3E library offers a wide variety of sequential cells, including flip-flops and latches. Each has
a data input and optional enable, clear, or preset. In this section, timing characteristics are presented for
a representative sample from the library. For more details, refer to the Fusion, IGLOO/e, and ProASIC3/E
Table 2-93 Combinatorial Cell Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Combinatorial Cell
Equation
Parameter
–2
–1
Std.
Units
INV
Y = !A
tPD
0.40
0.46
0.54
ns
AND2
Y = A B
tPD
0.47
0.54
0.63
ns
NAND2
Y = !(A B)
tPD
0.47
0.54
0.63
ns
OR2
Y = A + B
tPD
0.49
0.55
0.65
ns
NOR2
Y = !(A + B)
tPD
0.49
0.55
0.65
ns
XOR2
Y = A
Bt
PD
0.74
0.84
0.99
ns
MAJ3
Y = MAJ(A , B, C)
tPD
0.70
0.79
0.93
ns
XOR3
Y = A
B Ct
PD
0.87
1.00
1.17
ns
MUX2
Y = A !S + B S
tPD
0.51
0.58
0.68
ns
AND3
Y = A B C
tPD
0.56
0.64
0.75
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.
Figure 2-36 Sample of Sequential Cells
DQ
DFN1
Data
CLK
Out
D
Q
DFN1C1
Data
CLK
Out
CLR
DQ
DFI1E1P1
Data
CLK
Out
En
PRE
D
Q
DFN1E1
Data
CLK
Out
En
相关PDF资料
PDF描述
ASM43DSXS CONN EDGECARD 86POS DIP .156 SLD
ASM43DSEN CONN EDGECARD 86POS .156 EYELET
ASM43DSEH CONN EDGECARD 86POS .156 EYELET
ASM43DRXS CONN EDGECARD 86POS DIP .156 SLD
174469-3 CONN BACKSHELL/CABLE CLAMP 9POS
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