参数资料
型号: M1A3PE1500-FGG484
厂商: Microsemi SoC
文件页数: 143/162页
文件大小: 0K
描述: IC FPGA 1KB FLASH 1.5M 484-FBGA
标准包装: 40
系列: ProASIC3E
RAM 位总计: 276480
输入/输出数: 280
门数: 1500000
电源电压: 1.425 V ~ 1.575 V
安装类型: 表面贴装
工作温度: 0°C ~ 70°C
封装/外壳: 484-BGA
供应商设备封装: 484-FPBGA(23x23)
ProASIC3E Flash Family FPGAs
Revision 13
2-67
Global Resource Characteristics
A3PE600 Clock Tree Topology
Clock delays are device-specific. Figure 2-38 is an example of a global tree used for clock routing. The
global tree presented in Figure 2-38 is driven by a CCC located on the west side of the A3PE600 device.
It is used to drive all D-flip-flops in the device.
Global Tree Timing Characteristics
Global clock delays include the central rib delay, the spine delay, and the row delay. Delays do not
include I/O input buffer clock delays, as these are I/O standard–dependent, and the clock may be driven
and conditioned internally by the CCC module. For more details on clock conditioning capabilities, refer
page 2-68, and Table 2-97 on page 2-68 present minimum and maximum global clock delays within the
device. Minimum and maximum delays are measured with minimum and maximum loading.
Figure 2-38 Example of Global Tree Use in an A3PE600 Device for Clock Routing
Central
Global Rib
VersaTile
Rows
Global Spine
CCC
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