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参数资料
| 型号： | M30600E8GP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 16-BIT, OTPROM, 10 MHz, MICROCONTROLLER, PQFP100 |
| 封装： | 14 X 14 MM, 0.50 MM PITCH, PLASTIC, LQFP-100 |
| 文件页数： | 61/139页 |
| 文件大小： | 1782K |
| 代理商： | M30600E8GP |
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Mitsubishi microcomputers
M16C / 60 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
28
(8) Software wait
A software wait can be inserted by setting the wait bit (bit 7) of the processor mode register 1 (address
000516) (Note) and bits 4 to 7 of the chip select control register (address 000816).
A software wait is inserted in the internal ROM/RAM area and in the external memory area by setting the
wait bit of the processor mode register 1. When set to “0”, each bus cycle is executed in one BCLK cycle.
When set to “1”, each bus cycle is executed in two or three BCLK cycles. After the microcomputer has been
reset, this bit defaults to “0”. When set to “1”, bits 4 to 7 of the chip select control register are invalid and a
wait is applied to all external memory areas (two or three BCLK cycles). When VCC is in the range 2.7V to
4.0V, set the wait bit to “1”. However, this is not necessary if the oscillation frequency is less than 3MHz.
When the wait bit of the processor mode register 1 is “0”, software waits can be set independently for
each of the 4 areas selected using the chip select signal. Bits 4 to 7 of the chip select control register
_______
correspond to chip selects CS0 to CS3. When one of these bits is set to “1”, the bus cycle is executed in
one BCLK cycle. When set to “0”, the bus cycle is executed in two or three BCLK cycles. These bits
default to “0” after the microcomputer has been reset.
The SFR area is always accessed in two BCLK cycles regardless of the setting of these control bits. Also,
the corresponding bits of the chip select control register must be set to “0” if using the multiplex bus to
access the external memory area.
Table 1.11 shows the software wait and bus cycles. Figure 1.19 shows example bus timing when using
software waits.
Area
Bus status
Wait bit
Bits 4 to 7 of chip select
control register
Bus cycle
Invalid
1
2 BCLK cycles
External
memory
area
Separate bus
0
1
1 BCLK cycle
Separate bus
0
2 BCLK cycles
Separate bus
1
0 (Note)
2 BCLK cycles
Multiplex bus
0
0 (Note)
3 BCLK cycles
Multiplex bus
1
3 BCLK cycles
0 (Note)
SFR
Internal
ROM/RAM
0
Invalid
1 BCLK cycle
Invalid
2 BCLK cycles
Note: Always set to “0”.
Table 1.11. Software waits and bus cycles
Note: Before attempting to change the contents of the processor mode register 1, set bit 1 of the protect
register (address 000A16) to “1”.
Bus Control
相关PDF资料 |
PDF描述 |
|---|---|
| M30600M8-XXXGP | 16-BIT, MROM, MICROCONTROLLER, PQFP100 |
| M30610MCA-XXXGP | 16-BIT, MROM, 10 MHz, MICROCONTROLLER, PQFP100 |
| M30610ECFS | 16-BIT, UVPROM, 10 MHz, MICROCONTROLLER, CQCC100 |
| M30612M4A-XXXGP | 16-BIT, MROM, 10 MHz, MICROCONTROLLER, PQFP100 |
| M30610ECGP | 16-BIT, OTPROM, 10 MHz, MICROCONTROLLER, PQFP100 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| M30-6011046 | 制造商:Harwin 功能描述: |
| M30-6011506 | 功能描述:集管和线壳 15 + 15 DIL SMT PLUG RoHS:否 产品种类:1.0MM Rectangular Connectors 产品类型:Headers - Pin Strip 系列:DF50 触点类型:Pin (Male) 节距:1 mm 位置/触点数量:16 排数:1 安装风格:SMD/SMT 安装角:Right 端接类型:Solder 外壳材料:Liquid Crystal Polymer (LCP) 触点材料:Brass 触点电镀:Gold 制造商:Hirose Connector |
| M30-6011546 | 功能描述:集管和线壳 30P Male Dual Row Vertical SMT RoHS:否 产品种类:1.0MM Rectangular Connectors 产品类型:Headers - Pin Strip 系列:DF50 触点类型:Pin (Male) 节距:1 mm 位置/触点数量:16 排数:1 安装风格:SMD/SMT 安装角:Right 端接类型:Solder 外壳材料:Liquid Crystal Polymer (LCP) 触点材料:Brass 触点电镀:Gold 制造商:Hirose Connector |
| M30-6012046 | 制造商:Harwin 功能描述: |
| M3060C | 制造商:VISHAY 制造商全称:Vishay Siliconix 功能描述:Dual Common-Cathode Schottky Rectifier |
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