参数资料
型号: M30600E8GP
元件分类: 微控制器/微处理器
英文描述: 16-BIT, OTPROM, 10 MHz, MICROCONTROLLER, PQFP100
封装: 14 X 14 MM, 0.50 MM PITCH, PLASTIC, LQFP-100
文件页数: 86/139页
文件大小: 1782K
代理商: M30600E8GP
Mitsubishi microcomputers
M16C / 60 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMAC
50
DMAi request cause select register
Symbol
Address
When reset
DMiSL(i=0,1)
03B8 16,03BA16
00 16
Bit name
Function
R
Bit symbol
W
b7
b6
b5
b4
b3
b2
b1
b0
DMA request cause
select bit
DSEL0
DSEL1
DSEL2
DSEL3
Nothing is assigned.
These bits can neither be set nor reset. When read, the value of these bits is “0”.
Software DMA request bit
If software trigger is selected, a
DMA request is generated by
setting this bit to “1” (When read,
the value of this bit is always “0”)
DSR
DMAi control register
Symbol
Address
When reset
DMiCON(i=0,1)
002C 16, 003C16
00000X002
Bit name
Function
Bit symbol
R
W
b7
b6
b5
b4
b3
b2
b1
b0
Transfer unit bit select bit
0 : 16 bits
1 : 8 bits
DMBIT
DMASL
DMAS
DMAE
Repeat transfer mode
select bit
0 : Single transfer
1 : Repeat transfer
DMA request bit (Note 1)
0 : DMA not requested
1 : DMA requested
0 : Disabled
1 : Enabled
0 : Fixed
1 : Forward
DMA enable bit
Source address direction
select bit (Note 3)
Destination address
direction select bit (Note 3)
0 : Fixed
1 : Forward
DSD
DAD
Nothing is assigned.
These bits can neither be set nor reset. When read, the value of these bits is “0”.
Note 1: DMA request can be cleared by resetting the bit.
Note 2: This bit can only be set to “0”.
Note 3: Source address direction select bit and destination address direction select bit
cannot be set to “1” simultaneously.
b3 b2 b1 b0
0 0 0 0 : Falling edge of INT0 / INT1
pin (Note)
0 0 0 1 : Software trigger
0 0 1 0 : Timer A0
0 0 1 1 : Timer A1
0 1 0 0 : Timer A2
0 1 0 1 : Timer A3
0 1 1 0 : Timer A4
0 1 1 1 : Timer B0
1 0 0 0 : Timer B1
1 0 0 1 : Timer B2
1 0 1 0 : UART0 transmit
1 0 1 1 : UART0 receive
1 1 0 0 : UART1 transmit
1 1 0 1 : UART1 receive
1 1 1 0 : A-D conversion
1 1 1 1 : Inhibited
Note: Address 03B816 is for INT0; address 03BA16 is for INT1.
(Note 2)
Figure 1.34. Configuration of DMAC register (1)
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