
Flash Memory
264
Mitsubishi microcomputers
M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Under
development
Preliminary Specifications Rev.1.0
Specifications in this manual are tentative and subject to change.
Figure 1.27.2. ROMCP Register
Figure 1.27.3. Address for ID Code Stored
Symbol
Address
Value when shipped
ROMCP
0FFFFF16
FF16 (Note 4)
ROM code protect control address
Bit name
Function
Bit symbol
b7
b6
b5
b4
b3
b2
b1
b0
00: Removes protect
01:
10:
11:
00:
01:
10:
11: Protect disabled
ROM code protect reset
bit (Note 2, Note 4)
ROM code protect level
1 set bit
(Note 1, Note 3, Note 4)
ROMCR
ROMCP1
b5 b4
b7 b6
1
Reserved bit
Set this bit to “1”
Reserved bit
Set this bit to “1”
Reserved bit
Set this bit to “1”
Reserved bit
Set this bit to “1”
Enables ROOMCP1 bit
}
Protect enabled
}
Note 1: If the ROMCR bits are set to other than ‘002’ and the ROMCP1 bits are set to other than ‘112’ (
ROM code protect enabled), the flash memory is disabled against reading and rewriting in
parallel input/output mode.
Note 2: If the ROMCR bits are set to ‘002’ when the ROMCR bits are other than ‘002’ and the ROMCP1
bits are other than ‘112,’ ROM code protect level 1 is removed. However, because the ROMCR
bits cannot be modified during parallel input/output mode, they need to be modified in standard
serial input/output or other modes.
Note 3: The ROMCP1 bits are effective when the ROMCR bits are ‘012,’ ‘102,’ or ‘112.’
Note 4: Once any of these bits is cleared to “0”, it cannot be set back to “1”. If a memory block that
contains the ROMCP register is erased, the ROMCP register is set to ‘FF16.’
1
RW
Reset vector
Watchdog timer vector
Single step vector
Address match vector
BRK instruction vector
Overflow vector
Undefined instruction vector
ID7
ID6
ID5
ID4
ID3
ID2
ID1
DBC vector
NMI vector
0FFFFF16 to 0FFFFC16
0FFFFB16 to 0FFFF816
0FFFF716 to 0FFFF416
0FFFF316 to 0FFFF016
0FFFEF16 to 0FFFEC16
0FFFEB16 to 0FFFE816
0FFFE716 to 0FFFE416
0FFFE316 to 0FFFE016
0FFFDF16 to 0FFFDC16
4 bytes
Address
ROMCP