
Timers (Timer B)
128
Mitsubishi microcomputers
M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Under
development
Preliminary Specifications Rev.1.0
Specifications in this manual are tentative and subject to change.
Figure 1.15.8. Operation timing when measuring a pulse width
Measurement pulse
“H”
Count source
Timing at which counter
reaches “000016”
“1”
Transfer
(measured value)
Transfer
(measured value)
“L”
“0”
“1”
“0”
(Note 1)
Transfer
(measured
value)
(Note 1)
(Note 2)
Transfer
(indeterminate
value)
Reload register
counter
transfer timing
TBiS bit
TBiIC register's
IR bit
TBiMR register's
MR3 bit
Note 1: Counter is initialized at completion of measurement.
Note 2: Timer has overflowed.
Note 3: This timing diagram is for the case where the TBiMR register's MR1 to MR0 bits are “102” (measure the interval
from a falling edge to the next rising edge and the interval from a rising edge to the next falling edge of the
measurement pulse).
The TB0S to TB2S bits are assigned to the TABSR register's bit 5 to bit 7, and the TB3S to TB5S bits
are assigned to the TBSR register's bit 5 to bit 7.
Set to “0” upon accepting an interrupt request or by
writing in program
i = 0 to 5
Figure 1.15.7. Operation timing when measuring a pulse period
Count source
Measurement pulse
TBiS bit
TBiIC register's
IR bit
Timing at which counter
reaches “000016”
“H”
“1”
Transfer
(indeterminate value)
“L”
“0”
TBiMR register's
MR3 bit
“1”
“0”
Note 1: Counter is initialized at completion of measurement.
Note 2: Timer has overflowed.
Note 3: This timing diagram is for the case where the TBiMR register's MR1 to MR0 bits are “002” (measure the interval
from falling edge to falling edge of the measurement pulse).
(Note 1)
(Note 2)
Transfer
(measured value)
“1”
Reload register
counter
transfer timing
The TB0S to TB2S bits are assigned to the TABSR register's bit 5 to bit 7, and the TB3S to TB5S bits
are assigned to the TBSR register's bit 5 to bit 7.
Set to “0” upon accepting an interrupt request or by writing in
program
i = 0 to 5