- 您现在的位置：买卖IC网 > PDF目录69009 > M306N5FCTGP 16-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQFP100 PDF资料下载
参数资料
| 型号： | M306N5FCTGP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 16-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQFP100 |
| 封装： | 14 X 14 MM, 0.50 MM PITCH, PLASTIC, LQFP-100 |
| 文件页数： | 14/63页 |
| 文件大小： | 825K |
| 代理商： | M306N5FCTGP |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页当前第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页
Usage precaution
Mitsubishi microcomputers
M16C / 62M (80-pin version) Group
(Low voltage version)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
18
(4) External interrupt
_______
________
When the polarity of the INT0 to INT2 pins is changed, the interrupt request bit is sometimes set
to "1". After changing the polarity, set the interrupt request bit to "0".
Example 1:
INT_SWITCH1:
FCLR
I
; Disable interrupts.
AND.B
#00h, 0055h
; Clear TA0IC int. priority level and int. request bit.
NOP
FSET
I
; Enable interrupts.
Example 2:
INT_SWITCH2:
FCLR
I
; Disable interrupts.
AND.B
#00h, 0055h
; Clear TA0IC int. priority level and int. request bit.
MOV.W MEM, R0
; Dummy read.
FSET
I
; Enable interrupts.
Example 3:
INT_SWITCH3:
PUSHC FLG
; Push Flag register onto stack
FCLR
I
; Disable interrupts.
AND.B
#00h, 0055h
; Clear TA0IC int. priority level and int. request bit.
POPC
FLG
; Enable interrupts.
The reason why two NOP instructions or dummy read are inserted before FSET I in Examples 1 and 2 is
to prevent the interrupt enable flag I from being set before the interrupt control register is rewritten due to
effects of the instruction queue.
(5) Rewrite the interrupt control register
To rewrite the interrupt control register, do so at a point that does not generate the interrupt
request for that register. If there is possibility of the interrupt request occur, rewrite the interrupt
control register after the interrupt is disabled. The program examples are described as follow:
When a instruction to rewrite the interrupt control register is executed but the interrupt is disabled,
the interrupt request bit is not set sometimes even if the interrupt request for that register has
been generated. This will depend on the instruction. If this creates problems, use the below
instructions to change the register.
Instructions : AND, OR, BCLR, BSET
Noise
(1) Insert bypass capacitor between VCC and VSS pin for noise and latch up countermeasure.
Insert bypass capacitor (about 0.1
F) and connect short and wide line between VCC and VSS
lines.
相关PDF资料 |
PDF描述 |
|---|---|
| M306N5FCFP | 16-BIT, FLASH, 24 MHz, MICROCONTROLLER, PQFP100 |
| M306N5FCVFP | 16-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQFP100 |
| M306N5FCVGP | 16-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQFP100 |
| M306N5MCT-XXXGP | 16-BIT, MROM, 20 MHz, MICROCONTROLLER, PQFP100 |
| M306V0ME-XXXFP | 16-BIT, MROM, MICROCONTROLLER, PQFP100 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| M306N5FCVFP | 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:Renesas MCU |
| M306N5FCVGP | 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:Renesas MCU |
| M306N5MCT-XXXFP | 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:Renesas MCU |
| M306N5MCT-XXXGP | 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:Renesas MCU |
| M306N5MCV-XXXFP | 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:Renesas MCU |
发布紧急采购，3分钟左右您将得到回复。