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参数资料
| 型号： | M32000D4BFP-80 |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 80 MHz, MICROCONTROLLER, PQFP100 |
| 封装： | 14 X 20 MM, 0.65 MM PITCH, PLASTIC, LQFP-100 |
| 文件页数： | 14/44页 |
| 文件大小： | 448K |
| 代理商： | M32000D4BFP-80 |
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SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
M32000D4BFP-80
21
Fig. 18 Automatic idle cycle insertion between consecutive read
and write cycles
__
When an "L" level is input to DC, the next bus cycle is processed and
wait cycles are inserted until this point. When a write cycle comes
immediately after a read cycle, the M32000D4BFP-80 inserts an idle
cycle to prevent a collision with data on the system bus. The same
applies to write cycles (burst write access) immediately after a burst
read cycle.
Fig. 17 Read/write timing (two one-wait accesses)
"H"
idle
read
CLKIN
BS
A8 - A30
SID, ST
BCH, BCL
BURST
D0 - D15
DC
R/W
idle
read
"H"
idle
write
idle
write
CLKIN
BS
A8 - A30
SID, ST
BCH, BCL
BURST
D0 - D15
DC
R/W
"Hi-Z"
Note: "Hi-Z" means high-impedance, and
indicates sampling timing.
Keep DC signal at the "H" level when waits are inserted.
"H"
idle
CLKIN
BS
A8 - A30
SID, ST
BCH, BCL
BURST
D0 - D15
DC
R/W
idle
read
write
idle
"Hi-Z"
Note: "Hi-Z" means high-impedance, and
indicates sampling timing.
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