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参数资料
| 型号： | M34238MK-XXXGP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 4-BIT, MROM, 4 MHz, MICROCONTROLLER, PDSO20 |
| 封装： | PLASTIC, SOP-20 |
| 文件页数： | 3/41页 |
| 文件大小： | 243K |
| 代理商： | M34238MK-XXXGP |
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MITSUBISHI MICROCOMPUTERS
4238 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS
10
INSTRUCTION CLOCK SWITCH FUNCTION
The M34238MK-XXXGP has an instruction clock switch function to
select the divide-by-4 of system clock (f(XIN)/4) or divide-by-32 of
system clock (f(XIN)/32) as the instruction clock.
Instruction clock f(XIN)/32 is selected by default when the system is
returned from a RAM back-up state or standby state or released from
reset. The instruction clock can be switched to f(XIN)/4 by executing
the CCK instruction at address 0 in page 0. However, once the in-
struction clock is switched to f(XIN)/4, it cannot be switched back to
f(XIN)/32 again.
Note that the selective range of system clock signal f(XIN) varies de-
pending on whether to use the CCK instruction as shown below.
CCK instruction
Used
Not used
Instruction clock
f(XIN)/4
f(XIN)/32
f(XIN) frequency
300kHz to 500kHz
2.4MHz to 4.0MHz
Table 1 Selective range of f(XIN) frequency
MACHINE CYCLE COUNT FUNCTION
The M34238MK-XXXGP has a function to count the machine cycles
(instruction clock periods). When the port CARR output latch is set to
“1” with the OCRA instruction, the system starts counting beginning
with the next machine cycle. The count value is controlled by a ma-
chine cycle count value select register MC. By writing a value to the
register MC with the TMCA instruction, the 64 machine cycles or
1024 machine cycles are selected as the count value. Each time the
number of selected machine cycles is reached, the machine cycle
counter overflow flag MF is set to “1”. The machine cycle counter al-
ways remains active while the microcomputer is operating.
The state of flag MF can be examined with the SNZMF
instruction.The flag MF is cleared to “0” with the OCRA or SNZMF
instruction.
The register MC is cleared to “0” when the system is returned from a
standby state or RAM back-up state or released from a reset.
Fig. 14 Machine cycle count value select register
Machine cycle count value select register MC
(at reset : 02, at RAM back-up : 02, W)
Machine cycle count value select bit
Count value
MC0
0
1
64 machine cycles selected
1024 machine cycles selected
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