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参数资料
| 型号： | M34238MK-XXXGP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 4-BIT, MROM, 4 MHz, MICROCONTROLLER, PDSO20 |
| 封装： | PLASTIC, SOP-20 |
| 文件页数： | 31/41页 |
| 文件大小： | 243K |
| 代理商： | M34238MK-XXXGP |
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MITSUBISHI MICROCOMPUTERS
4238 Group
PROM VERSION OF M34238MK-XXXGP
36
5
Setting of unused pins
Set the unused pins as shown in Table 3.
Table 3 Setting of unused pins
Notes 1. (Notes when the port D output latch is set to “0” and pins
are open)
Port D output latches are set to “1” when system is re-
leased from reset, and is returned from the RAM back-
up state and standby state. Clear the port D output
latches to “0” by software.
The output level of pins is undefined until the port D out-
put latches are set to “0”, and the supply current may be
increased.
To set the output latch periodically by software is recom-
mended because value of output latch may change by
noise or a program run-away (caused by noise).
(Note when connecting to VSS)
Connect the unused pins to VSS at the shortest possible
distance (within 20 mm) using the thickest possible wire
in order to prevent noise.
2. It is only for PROM version. When using Mask ROM ver-
sion, connect CNVSS to VSS.
Pin
XOUT
______
RESET
D0 – D7
E, G0 – G3
CNVSS
Setting
Open
Set the port D output latches to “0” and open, or
connect to VSS (Note 1).
Open
Connect to VSS or open (Note 2)
6
Notes on the stack pointer (SP)
Stack pointer transition diagram
The stack register (SK) is made up of four stages. The 2-bit stack
pointer (SP) specifies stack register nesting. The initial value of the
stack pointer is “3”. Figure 7 is a stack pointer transition diagram.
When a call is made, the stack pointer is incremented by “1” and the
contents of the program counter is then stored in the stack register
specified by the stack pointer. When a return is made, the contents
temporarily stored in the stack register is returned to the program
counter, and the value of the stack pointer is then decremented by
“1”. If a call is made when all four stages of the stack register have
been used (SP=3), the data in the first stage of the stack register is
destroyed.
Fig. 7 Stack pointer transition diagram
SP = 3
When system is released from reset (Note)
Note : Likewise, SP = 3 when system is returned from
RAM back-up state and standby state.
SP = 1
SP = 0
SP = 2
return
call
SP : Stack pointer
DATA REQUIRED FOR ROM ORDERING
Please submit the following data for ROM orders.
(1)M34238EK-XXXGP ROM Programming Confirmation Form .... 1
(2)PROM data ..................................................................... EPROM
(Submit three sets of EPROMs with the same data)
(3)Mark Specification Form ............................................................ 1
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