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参数资料
型号： M34509G4HFP
元件分类： 微控制器/微处理器
英文描述： 4-BIT, OTPROM, 6 MHz, MICROCONTROLLER, PDSO24
封装： 5.30 X 10.10 MM, 0.80 MM PITCH, PLASTIC, SSOP-24
文件页数： 3/143页
文件大小： 1056K
代理商： M34509G4HFP
TABP p (Transfer data to Accumulator and register B from Program memory in page p)
00100p4
p3
p2
p1
p0
0p
13
–
Grouping:
Arithmetic operation
Description: Transfers bits 7 to 4 to register B and bits 3 to 0 to register A. These bits 7
to 0 are the ROM pattern in address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified
by registers A and D in page p. When UPTF is 1, Transfers bits 9, 8 to the
low-order 2 bits (DR1, DR0) of register D, and “0” is stored to the least
significant bit (DR2) of register D.
When this instruction is executed, 1 stage of stack register (SK) is used.
Note:
p is 0 to 31.
When this instruction is executed, be careful not to over the stack be-
cause 1 stage of stack register is used.
Operation:
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← p
(PCL) ← (DR2–DR0, A3–A0)
(B) ← (ROM(PC))7–4
(A) ← (ROM(PC))3–0
(UPTF) ← 1
(DR1, DR0) ← (ROM(PC))9, 8
(DR2) ← 0
(PC) ← (SK(SP))
(SP) ← (SP) – 1
TAD (Transfer data to Accumulator from register D)
0001010001
051
11
–
Grouping:
Register to register transfer
Description: Transfers the contents of register D to the
low-order 3 bits (A2–A0) of register A.
Note:
When this instruction is executed, “0” is
stored to the bit 3 (A3) of register A.
Operation:
(A2–A0) ← (DR2–DR0)
(A3) ← 0
8
+p
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TABPS (Transfer data to Accumulator and register B from Pre-Scaler)
1001110101
275
11
–
Grouping:
Timer operation
Description: Transfers the high-order 4 bits of prescaler
to register B.
Transfers the low-order 4 bits of prescaler to
register A.
Operation:
(B) ← (TPS7–TPS4)
(A) ← (TPS3–TPS0)
TABSI (Transfer data to Accumulator and register B from register SI)
1001111000
278
11
–
Grouping:
Serial interface operation
Description: Transfers the high-order 4 bits of serial inter-
face register SI to register B, and transfers
the low-order 4 bits of serial interface regis-
ter SI to register A.
Operation:
(B) ← (SI7–SI4) (A) ← (SI3–SI0)
Skip condition
Number of
cycles
Number of
words
Instruction
code
D9
D0
Flag CY
2
16
Skip condition
Number of
cycles
Number of
words
Instruction
code
D9
D0
Flag CY
2
16
Skip condition
Number of
cycles
Number of
words
Instruction
code
D9
D0
Flag CY
2
16
Skip condition
Number of
cycles
Number of
words
Instruction
code
D9
D0
Flag CY
2
16
Rev.1.03
2009.07.27
page 100 of 140
REJ03B0147-0109
4509 Group
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