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| 型号： | M34509G4HFP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 4-BIT, OTPROM, 6 MHz, MICROCONTROLLER, PDSO24 |
| 封装： | 5.30 X 10.10 MM, 0.80 MM PITCH, PLASTIC, SSOP-24 |
| 文件页数： | 69/143页 |
| 文件大小： | 1056K |
| 代理商： | M34509G4HFP |
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4509 Group
Rev.1.03
2009.07.27
page 31 of 140
REJ03B0147-0103
(5) Count start synchronization circuit (timer 1)
Timer 1 has the count start synchronous circuit which synchronizes
the input of INT pin, and can start the timer count operation.
Timer 1 count start synchronous circuit function can be selected af-
ter timer 1 control by INT pin is enabled by setting the bit 0 of
register I1 to “1” and its function is selected by setting the bit 1 of
register W5 to “1”.
When timer 1 count start synchronous circuit is used, the count start
synchronous circuit is set, the count source is input to timer by input-
ting valid waveform to INT pin.
The valid waveform of INT pin to set the count start synchronous cir-
cuit is the same as the external interrupt activated condition.
Once set, the count start synchronous circuit is cleared by clearing
the bit I10 to “0” or system reset.
However, when the count auto-stop circuit is selected (W22 = “1”),
the count start synchronous circuit is cleared (auto-stop) at the timer
1 underflow.
(6) Count auto-stop circuit (timer 1)
Timer 1 has the count auto-stop circuit which is used to stop timer 1
automatically by the timer 1 underflow when the count start synchro-
nous circuit is used.
The count auto-stop circuit is valid by setting the bit 2 of register W5
to “1”. It is cleared by the timer 1 underflow and the count source to
timer 1 is stopped.
This function is valid only when the timer 1 count start synchronous
circuit is selected.
(7) INT pin input period count circuit (timer 2)
Timer 2 has the INT pin input period count circuit to count the valid
waveform input interval of the INT pin.
When bit 1 of register W6 is set to “1”, the INT pin input period count
circuit of timer 2 becomes valid, and the count source is input. The
count source input is stopped by the next input of valid waveform to
the INT pin.
Then, every a valid waveform is input to the INT pin, start/stop of the
count source input is alternately repeated.
A valid waveform of the INT pin input is the same as the activated
condition of an external interrupt.
The INT pin input period count circuit set once is cleared by setting
the INT pin input to be disabled state. The INT pin input can be dis-
abled by clearing bit 3 of register I1 to “0”.
(8) Timer input/output pin (P12/CNTR0 pin, P11/
CNTR1 pin)
CNTR0 pin is used to input the timer 2 count source and output the
PWM1 signal generated by timer 1.
CNTR1 pin is used to input the timer 1 count source and output the
PWM2 signal generated by timer 2.
The P12/CNTR0 pin function can be selected by bit 3 of register W5.
The P11/CNTR1 pin function can be selected by bit 3 of register W6.
When the CNTR0 input is selected for timer 2 count source, timer 2
counts the falling or rising waveform of CNTR0 input. The count
edge is selected by bit 0 of register W5.
When the CNTR1 input is selected for timer 1 count source, timer 1
counts the falling or rising waveform of CNTR1 input. The count
edge is selected by bit 0 of register W6.
(4) Timer 2 (interrupt function)
Timer 2 is an 8-bit binary down counter with two timer 2 reload regis-
ters (R2L, R2H). Data can be set simultaneously in timer 2 and the
reload register R2L with the T2AB instruction. Data can be set in the
reload register R2H with the T2HAB instruction. The contents of re-
load register R2L set with the T2AB instruction can be set to timer 2
again with the T2R2L instruction. Data can be read from timer 2 with
the TAB2 instruction.
Stop counting and then execute the T2AB or TAB2 instruction to read
or set timer 2 data.
When executing the T2HAB instruction to set data to reload register
R2H while timer 2 is operating, avoid a timing when timer 2
underflows.
Timer 2 starts counting after the following process;
set data in timer 2
set count source by bits 0 and 1 of register W2, and
set the bit 2 of register W2 to “1.”
When a value set in reload register R2L is n and a value set in re-
load register R2H is m, timer 2 divides the count source signal by n +
1 or m + 1 (n = 0 to 255, m = 0 to 255).
Once count is started, when timer 2 underflows (the next count pulse
is input after the contents of timer 2 becomes “0”), the timer 2 inter-
rupt request flag (T2F) is set to “1,” new data is loaded from reload
register R2L, and count continues (auto-reload function).
<Bit 3 of register W2 = “0” (PWM2 function invalid)>
Once count is started, when timer 2 underflows (the next count pulse
is input after the contents of timer 2 becomes “0”), the timer 2 inter-
rupt request flag (T2F) is set to “1,” new data is loaded from reload
register R2L, and count continues (auto-reload function).
<Bit 3 of register W2 = “1” (PWM2 function valid)>
Timer 2 generates the PWM2 signal of the “L” interval set as reload
register R2L, and the “H” interval set as reload register R2H. The
PWM2 signal generated by timer 2 is output from CNTR1 pin by set-
ting “1” to bit 3 of register W6.
PWM2 output to CNTR1 pin combined with timer 1 can be controlled
by setting the bit 2 of register W6 to “1.”
Input period of INT pin by timer 2 can be counted by setting the bit 1
of register W6 to “1.”
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