参数资料
型号: M37271EFSP
元件分类: 微控制器/微处理器
英文描述: 8-BIT, OTPROM, 8.1 MHz, MICROCONTROLLER, PDIP52
封装: 0.600 INCH, 1.78 MM PITCH, PLASTIC, SDIP-52
文件页数: 42/64页
文件大小: 1252K
代理商: M37271EFSP
MITSUBISHI MICROCOMPUTERS
M37271MF-XXXSP
M37271EF-XXXSP, M37271EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
44
7
MST
0
I2C status register
(S1 : address 00F816)
Last receive bit (Note)
0 : Last bit = “0”
1 : Last bit = “1”
General call detecting flag
(Note)
0 : No general call detected
1 : General call detected
Slave address comparison flag
(Note)
0 : Address disagreement
1 : Address agreement
Arbitration lost detecting flag
(Note)
0 : Not detected
1 : Detected
I2C-BUS interface interrupt
request bit
0 : Interrupt request issued
1 : No interrupt request
issued
Bus busy flag
0 : Bus free
1 : Bus busy
Communication mode
specification bits
00 : Slave receive mode
01 : Slave transmit mode
10 : Master receive mode
11 : Master transmit mode
TRX BB PIN AL AAS AD0 LRB
Note: These bit and flags can be read out but cannot
be written.
(6) START Condition Generating Method
When the ES0 bit of the I2C control register (address 00F916) is “1,”
execute a write instruction to the I2C status register (address 00F816)
for setting the MST, TRX and BB bits to “1.” Then a START condi-
tion occurs. After that, the bit counter becomes “0002” and an SCL
for 1 byte is output. The START condition generating timing and BB
bit set timing are different in the standard clock mode and the high-
speed clock mode. Refer to Figure 46, the START condition generat-
ing timing diagram, and Table 8, the START condition/STOP condi-
tion generating timing table.
(7) STOP Condition Generating Method
When the ES0 bit of the I2C control register (address 00F916) is “1,”
execute a write instruction to the I2C status register (address 00F816)
for setting the MST bit and the TRX bit to “1” and the BB bit to “0”.
Then a STOP condition occurs. The STOP condition generating tim-
ing and the BB flag reset timing are different in the standard clock
mode and the high-speed clock mode. Refer to Figure 47, the STOP
condition generating timing diagram, and Table 8, the START condi-
tion/STOP condition generating timing table.
Table 8. START condition/STOP condition generating timing
table
Fig. 46. START condition generating timing diagram
Fig. 47. STOP condition generating timing diagram
Fig. 45. Interrupt request signal generating timing
Fig. 44. Structure of I2C status register
SCL
PIN
IICIRQ
I2C status register
write signal
Set time for
BB flag
Hold time
Setup
time
SCL
SDA
BB flag
Setup
time
I2C status register
write signal
Reset time for
BB flag
Hold time
Setup
time
SCL
SDA
BB flag
Item
Setup time
Hold time
Set/reset time
for BB flag
Standard clock mode
5.0
s (20 cycles)
5.0
s (20 cycles)
3.0
s (12 cycles)
High-speed clock mode
2.5
s (10 cycles)
2.5
s (10 cycles)
1.5
s (6 cycles)
Note: Absolute time at
φ = 4 MHz. The value in parentheses de-
notes the number of
φ cycles.
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