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参数资料
型号： M37641F8FP
元件分类： 微控制器/微处理器
英文描述： 8-BIT, FLASH, 12 MHz, MICROCONTROLLER, PQFP80
封装： 14 X 20 MM, 0.80 MM, PLASTIC, QFP-80
文件页数： 114/140页
文件大小： 1694K
代理商： M37641F8FP
7641 Group
Rev.4.00
Aug 28, 2006
page 73 of 135
REJ03B0191-0400
Notes
Reset
C
P
M
A
4
“1
”←
→
“0
”
FSC0
“0”
←→“1”
XIN clock oscillating,
XCIN clock stopped,
Frequency synthesizer
clock stopped,
CPMA = 0C, FSC = 60
φ = f(XIN/4)
1 : Switch the mode by the allows shown between the mode blocks. (Do not switch between the modes directly without an allow.)
2 : In Stop mode, though the frequency synthesizer is not automatically disabled, the oscillator which sends clocks to the frequency
synthesizer stops. Set the system clock and disable the frequency synthesizer before execution of the STP instruction.
3 :
φ = f(XIN)/2 can be also used by setting the XIN divider select bit (CCR7) to “1”. Then this diagram also applies to that case.
4 : The frequency synthesizer’s input can be selected between XIN input and XCIN input regardless of the system clock. This diagram
assumes the frequency synthesizer’s input to be the system clock. Enable the oscillator to be used for the frequency synthesizer’s input
before enabling the frequency synthesizer.
5 : Select the XCIN input as the frequency synthesizer’s input by setting the frequency synthesizer input bit (FSC3) to “1” before stopping XIN
oscillation.
(Note 3)
XIN clock oscillating,
XCIN clock stopped,
Frequency synthesizer
clock oscillating,
CPMA = 0C, FSC = 41
φ = f(XIN/4)
CPMA6
“0”
←→“1”
XIN clock oscillating,
XCIN clock stopped,
Frequency synthesizer
clock oscillating,
CPMA = 4C, FSC = 41
φ = f(PLL)/2
(Note 3)
(Note 4)
WAIT
STOP
(Note 2)
WAIT
FSC0
“0”
←→“1”
XIN clock oscillating,
XCIN clock oscillating,
Frequency synthesizer
clock stopped,
CPMA = 1C, FSC = 60
φ = f(XIN/4) (Note 3)
XIN clock oscillating,
XCIN clock oscillating,
Frequency synthesizer
clock oscillating,
CPMA = 1C, FSC = 41
φ = f(XIN/4)
CPMA6
“0”
←→“1”
XIN clock oscillating,
XCIN clock oscillating,
Frequency synthesizer
clock oscillating,
CPMA = 5C, FSC = 41
φ = f(PLL)/2
(Note 3)
(Note 4)
(Note 2)
WAIT
STOP
WAIT
C
P
M
A
7
“1
”←
→
“0
”
FSC0
“0”
←→“1”
XIN clock oscillating,
XCIN clock oscillating,
Frequency synthesizer
clock stopped,
CPMA = 9C, FSC = 60
φ = f(XCIN/2)
XIN clock oscillating,
XCIN clock oscillating,
Frequency synthesizer
clock oscillating,
CPMA = 9C, FSC = 41
φ = f(XCIN/2)
CPMA6
“0”
←→“1”
XIN clock oscillating,
XCIN clock oscillating,
Frequency synthesizer
clock oscillating,
CPMA = DC, FSC = 41
φ = f(PLL)/2
(Note 4)
(Note 2)
WAIT
STOP
WAIT
C
P
M
A
5
“1
”←
→
“0
”
FSC0
“0”
←→“1”
XIN clock stopped,
XCIN clock oscillating,
Frequency synthesizer
clock stopped,
CPMA = BC, FSC = 68
φ = f(XCIN/2)
XIN clock stopped,
XCIN clock oscillating,
Frequency synthesizer
clock oscillating,
CPMA = BC, FSC = 49
φ = f(XCIN/2)
CPMA6
“0”
←→“1”
XIN clock stopped,
XCIN clock oscillating,
Frequency synthesizer
clock oscillating,
CPMA = FC, FSC = 49
φ = f(PLL)/2
(Note 2)
WAIT
STOP
WAIT
(Note 5)
(Note 4)
Remarks : This diagram assumes that:
Stack page is page 1
In single-chip mode
(Depending on the CPU mode register A)
φ expresses the internal clock.
Fig. 68 State transitions of clock
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