参数资料
型号: M37641F8FP
元件分类: 微控制器/微处理器
英文描述: 8-BIT, FLASH, 12 MHz, MICROCONTROLLER, PQFP80
封装: 14 X 20 MM, 0.80 MM, PLASTIC, QFP-80
文件页数: 92/140页
文件大小: 1694K
代理商: M37641F8FP
7641 Group
Rev.4.00
Aug 28, 2006
page 53 of 135
REJ03B0191-0400
[USB Endpoint 0 IN Control Register ] IN_CSR
This register contains the control and status information of the
endpoint 0. This USB FCU sets the OUT_PKT_RDY flag to “1”
upon having received a data packet in the OUT FIFO. When read-
ing its one data packet from the OUT FIFO, be sure to set this flag
to “0”.
After a SETUP token is received, the MCU is in the “decode wait
state ” until the OUT_PKT_RDY flag is cleared. If the
OUT_PKT_RDY flag is not cleared (indicating that the host re-
quest has not been successfully decoded), the USB FCU keep
returning a NAK to the host for all IN/OUT tokens.
Set the IN_PKT_RDY bit to “1” after the data packet has been
written to the IN FIFO. If this bit is set to “1” even though nothing
has been written to the IN FIFO, a “0” length data (NULL packet)
is sent to the host. The SEND_STALL bit is for sending a STALL to
the host if an unsupported request is received by the USB FCU.
This bit must be set to “1”. When the OUT_PKT_RDY flag is set to
“0” for request reception, the USB FCU transmits a STALL signal
to the Host CPU. Perform the following three processes simulta-
neously:
Set SEND_STALL bit to “1”
Set DATA_END bit to “1”
Set OUT_PKT_RDY flag to “0” by setting SERVICED_OUT
_PKT_RDY bit to “1”.
Note that if “0” is written to the SEND_STALL bit before the
CLEAR_FEATURE (endpoint STALL) request has been received,
the next STALL will not be generated.
The DATA_END bit informs the USB FCU of the completion of the
process indicated in the SETUP packet. Set this bit to “1” when
the process requested in the SETUP packet is completed. (Con-
trol Read Transfer: set this bit after writing all of the requested
data to the FIFO; Control Write Transfer: set this bit to “1” after
reading all of the requested data from the FIFO.) When this bit is
“1”, the host request is ignored and a STALL is returned. After the
status phase process is completed, the USB FCU automatically
clears it to “0”.
USB endpoint 0 IN control register (address 005916)
IN_CSR
OUT_PKT_RDY flag (IN0CSR0)
0: Except the following condition (Cleared to “0” by writing “1” into
SERVICED_OUT_PKT_RDY bit)
1: End of a data packet reception
IN_PKT_RDY bit (IN0CSR1)
0: End of a data packet transmission
1: Write “1” at completion of writing a data packet into IN FIFO.
SEND_STALL bit (IN0CSR2)
0: Except the following condition
1: Transmitting STALL handshake signal
DATA_END bit (IN0CSR3)
0: Except the following condition (Cleared to “0” after completion of
status phase)
1: Write “1” at completion of writing or reading the last data packet
to/from FIFO.
FORCE_STALL flag (IN0CSR4)
0: Except the following condition
1: Protocol error detected
SETUP_END flag (IN0CSR5) (Note )
0: Except the following condition (Cleared to “0” by writing “1” into
SERVICED_SETUP_END bit)
1: Control transfer ends before the specific length of data is
transferred during the data phase.
SERVICED_OUT_PKT_RDY bit (IN0CSR6)
Writing “1” to this bit clears OUT_PKT_RDY flag to “0”.
SERVICED_SETUP_END bit (IN0CSR7)
Writing “1” to this bit clears SETUP_END flag to “0”.
b0
b7
Note: If this bit is set to “0”, stop accessing the FIFO to serve the previous setup transaction.
Fig. 46 Structure of USB endpoint 0 IN control register
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