参数资料
型号: M37641F8FP
元件分类: 微控制器/微处理器
英文描述: 8-BIT, FLASH, 12 MHz, MICROCONTROLLER, PQFP80
封装: 14 X 20 MM, 0.80 MM, PLASTIC, QFP-80
文件页数: 61/140页
文件大小: 1694K
代理商: M37641F8FP
7641 Group
Rev.4.00
Aug 28, 2006
page 25 of 135
REJ03B0191-0400
Fig. 20 Structure of timer X mode register
Timer X
Timer X is a 16-bit timer that can be selected in one of four modes.
The timer X’s internal clock and count source can be selected and
a write control is possible by using the timer X mode register.
In all modes the count operation can halt by setting the Timer X
Count Stop Bit to “1”. Additionally, each timer underflow sets the
Interrupt Request Bit to “1”.
(1) Timer Mode
The timer counts the SCSGCLK (Special Count Source Genera-
tor) or one of the internal clock
φ divided by 8, 16, 32, 64.
(2) Pulse Output Mode
Each time the timer underflows, a signal output from the CNTR0
pin is inverted. Except for this, the operation in pulse output mode
is the same as in timer mode.
When the CNTR0 Active Edge Switch Bit is “0”, the CNTR0 pin
starts pulses output beginning at “H”; when this bit is “1”, the
CNTR0 pin starts pulses output beginning at “L”.
When using a timer in this mode, set the port P43 direction regis-
ter to output mode.
(3) Event Counter Mode
The timer counts signals input through the CNTR0 pin.
Except for this, the operation in event counter mode is the same
as in timer mode.
When the CNTR0 Active Edge Switch Bit is “0”, the rising edge is
counted; when this bit is “1”, the falling edge is counted.
When using a timer in this mode, set the port P43 direction regis-
ter to input mode.
(4) Pulse Width Measurement Mode
When the CNTR0 Active Edge Switch Bit is “0”, the timer counts
while the input signal of CNTR0 pin is at “H”; when it is “1”, the
timer counts while the input signal of CNTR0 pin is at “L”.
The timer counts the SCSGCLK or one of the internal clock
φ di-
vided by 8, 16, 32, 64 as its count source.
When using a timer in this mode, set the port P43 direction regis-
ter to input mode.
s Notes
q Timer X Write Control
If the Timer X Write Control Bit is “1”, when the value is written in
the address of timer X, the value is loaded only in the latch. The
value in the latch is loaded in timer X after timer X underflows.
If the Timer X Write Control Bit is “0”, when the value is written in
the address of timer X, the value is loaded in the timer X and the
latch at the same time.
When the value is to be written in latch only, unexpected value
may be set in the high-order timer if the writing in high-order latch
and the underflow of timer X are performed at the same timing.
q CNTR0 Interrupt Active Edge Selection
The CNTR0 interrupt active edge depends on the selection of
CNTR0 Active Edge Switch Bit.
Timer X mode register (address 002716)
TXM
Timer X write control bit
0: Write value in latch and counter
1: Write value in latch only
Timer X count source select bits
b2b1
0 0:
φ / 8
0 1:
φ / 16
1 0:
φ / 32
1 1:
φ / 64
Timer X internal clock select bit
0:
φ / n (n = 8, 16, 32, 64)
1: SCSGCLK (Special Count Source Generator)
Timer X operating mode bits
b5b4
0 0: Timer mode
0 1: Pulse output mode
1 0: Event counter mode
1 1: Pulse width measurement mode
CNTR0 active edge switch bit
0: Count at rising edge in event counter mode
Start from “H” output in pulse output mode
Measure “H” pulse width in pulse width
measurement mode
Falling edge active for interrupt
1: Count at falling edge in event counter mode
Start from “L” output in pulse output mode
Measure “L” pulse width in pulse width
measurement mode
Rising edge active for interrupt
Timer X count stop bit
0: Count start
1: Count stop
b0
b7
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