参数资料
型号: M37733MHBXXXFP
元件分类: 微控制器/微处理器
英文描述: 16-BIT, MROM, 25 MHz, MICROCONTROLLER, PQFP80
封装: 14 X 20 MM, 0.80 MM PITCH, PLASTIC, QFP-80
文件页数: 5/89页
文件大小: 1506K
代理商: M37733MHBXXXFP
13
MITSUBISHI MICROCOMPUTERS
M37733MHBXXXFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
PRELIMINARY
Notice:
This
is not
a final
specification.
Some
parametric
limits
are
subject
to change.
Interrupt control registers
addresses
A-D/UART2 trans./rece. interrput control register
00007016
UART0 transmit interrput control register
00007116
UART0 receive interrput control register
00007216
UART1 transmit interrput control register
00007316
UART1 receive interrupt control register
00007416
Timer A0 interrupt control register
00007516
Timer A1 interrupt control register
00007616
Timer A2 interrupt control register
00007716
Timer A3 interrupt control register
00007816
Timer A4 interrupt control register
00007916
Timer B0 interrupt control register
00007A16
Timer B1 interrupt control register
00007B16
Timer B2 interrupt control register
00007C16
INT0
interrupt control register
00007D16
INT1
interrupt control register
00007E16
INT2
/Key input interrupt control register
00007F16
Table 2. Addresses of interrupt control registers
Interrupts caused by a BRK instruction and when dividing by zero
are software interrupts and are not included in this list.
Other interrupts previously mentioned are A-D converter, UART,
Timer, INT interrupts. The priority of these interrupts can be changed
by changing the interrupt priority level selection bits of the
corresponding interrupt control register with software.
Figure 8 shows a diagram of the interrupt priority detection circuit.
When an interrupt is caused, the each interrupt device compares its
own priority with the priority from above and if its own priority is higher,
then it sends the priority below and requests the interrupt. If the
priorities are the same, the one above has priority.
This comparison is repeated to select the interrupt with the highest
priority among the interrupts that are being requested. Finally the
selected interrupt is compared with the processor interrupt priority
level (IPL) contained in the processor status register (PS), and the
request is accepted if it is higher than IPL and the interrupt disable
flag (I) is “0”. The request is not accepted if flag I is “1”. The reset,
DBC
, and watchdog timer interrupts are not affected by the interrupt
disable flag (I).
When an interrupt is accepted, the contents of the processor status
register (PS) is saved to the stack and the interrupt disable flag (I) is
set to “1”.
Furthermore, the interrupt request bit of the accepted interrupt is
cleared to “0” and the processor interrupt priority level (IPL) in the
processor status register (PS) is replaced by the priority level of the
accepted interrupt.
Therefore, multiple interrupts are possible by resetting the interrupt
disable flag (I) to “0” and enable further interrupts.
For reset, DBC, watchdog timer, zero divide, and BRK instruction
interrupts, which do not have an interrupt control register, the
processor interrupt level (IPL) is set as shown in Table 3.
Priority detection is performed by latching the interrupt request bit
and interrupt priority level selection bits so that they do not change.
They are sampled at the first half and latched at the last half of the
operation code fetch cycle.
Because priority detection takes some time, no sampling pulse is
generated for a certain interval even if it is the next operation code
fetch cycle.
Fig. 8 Interrupt priority detection circuit
Fig. 7 Interrupt priority
Priority is determined by hardware
Watchdog
timer
DBC
Reset
A-D converter, UART, Timer, INT interrupts
Priority can be changed by software inside
1
2
3
4
timer
Watchdog
A-D/UART2
trans./rece.
Level 0
INT0
UART1 transmit
UART1 receive
UART0 transmit
UART0 receive
Timer B2
Timer B1
Timer B0
Timer A4
Timer A3
Timer A2
Timer A1
Timer A0
INT2
/Key input
INT1
IPL
Interrupt disable flag(I)
DBC
Reset
Interrupt request
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