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参数资料
| 型号： | M38039G4H-XXXKP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, 8.4 MHz, MICROCONTROLLER, PQFP64 |
| 封装： | 14 X 14 MM, 0.80 MM PITCH, PLASTIC, LQFP-64 |
| 文件页数： | 92/105页 |
| 文件大小： | 1416K |
| 代理商： | M38039G4H-XXXKP |
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REJ03B0166-0113 Rev.1.13
Aug 21, 2009
Page 85 of 100
3803 Group (Spec.H QzROM version)
3. Clock frequency during A/D conversion
The comparator consists of a capacity coupling, and a charge of
the capacity will be lost if the clock frequency is too low. Thus,
make sure the following during an A/D conversion.
f(XIN) is 500 kHz or more
Do not execute the STP instruction
4. Difference between at 8-bit reading in 10-bit A/D
mode and at 8-bit A/D mode
At 8-bit reading in the 10-bit A/D mode, “–1/2 LSB” correction
is not performed to the A/D conversion result.
In the 8-bit A/D mode, the A/D conversion characteristics is the
same as 3802 group’s characteristics because “–1/2 LSB”
correction is performed.
Notes on D/A Converter
1. VCC when using D/A converter
The D/A converter accuracy when VCC is 4.0 V or less differs
from that of when VCC is 4.0 V or more. When using the D/A
converter, we recommend using a VCC of 4.0 V or more.
2. D/Ai conversion register when not using D/A con-
verter
When a D/A converter is not used, set all values of the D/Ai
conversion registers (i = 1, 2) to “0016”. The initial value after
reset is “0016”.
Notes on Watchdog Timer
Make sure that the watchdog timer H does not underflow
while waiting Stop release, because the watchdog timer keeps
counting during that term.
When the STP instruction function selection bit has been set to
“1”, it is impossible to switch it to “0” by a program.
Notes on RESET Pin
Connecting capacitor
In case where the RESET signal rise time is long, connect a
ceramic capacitor or others across the RESET pin and the VSS
pin.
Use a 1000 pF or more capacitor for high frequency use. When
connecting the capacitor, note the following:
Make the length of the wiring which is connected to a
capacitor as short as possible.
Be sure to verify the operation of application products on the
user side.
<Reason>
If the several nanosecond or several ten nanosecond impulse
noise enters the RESET pin, it may cause a microcomputer
failure.
Notes on Low-speed Operation Mode
1. Using sub-clock
To use a sub-clock, fix bit 3 of the CPU mode register to “1” or
control the Rd (refer to Figure 83) resistance value to a certain
level to stabilize an oscillation. For resistance value of Rd,
consult the oscillator manufacturer.
Fig 83. Ceramic resonator circuit
<Reason>
When bit 3 of the CPU mode register is set to “0”, the sub-clock
oscillation may stop.
2. Switch between middle/high-speed mode and low-
speed mode
If you switch the mode between middle/high-speed and low-
speed, stabilize both XIN and XCIN oscillations. The sufficient
time is required for the sub clock to stabilize, especially
immediately after power on and at returning from stop mode.
When switching the mode between middle/high-speed and low-
speed, set the frequency on condition that f(XIN) > 3
×f(XCIN).
Quartz-Crystal Oscillator
When using the quartz-crystal oscillator of high frequency, such
as 16 MHz etc., it may be necessary to select a specific oscillator
with the specification demanded.
Notes on Restarting Oscillation
Restarting oscillation
Usually, when the MCU stops the clock oscillation by STP
instruction and the STP instruction has been released by an
external interrupt source, the fixed values of Timer 1 and
Prescaler 12 (Timer 1 = “0116”, Prescaler 12 = “FF16”) are
automatically reloaded in order for the oscillation to stabilize.
The user can inhibit the automatic setting by writing “1” to bit 0
of MISRG (address 001016).
However, by setting this bit to “1”, the previous values, set just
before the STP instruction was executed, will remain in Timer 1
and Prescaler 12. Therefore, you will need to set an appropriate
value to each register, in accordance with the oscillation
stabilizing time, before executing the STP instruction.
<Reason>
Oscillation will restart when an external interrupt is received.
However, internal clock
φ is supplied to the CPU only when
Timer 1 starts to underflow. This ensures time for the clock
oscillation using the ceramic resonators to be stabilized.
XCIN
XCOUT
CCIN
CCOUT
Rd
Rf
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