参数资料
型号: M38507F8AFP
元件分类: 微控制器/微处理器
英文描述: 8-BIT, FLASH, 6.25 MHz, MICROCONTROLLER, PDSO42
封装: 8.40 X 17.50 MM, 0.80 MM PITCH, PLASTIC, SSOP-42
文件页数: 11/59页
文件大小: 885K
代理商: M38507F8AFP
Rev.2.13
Apr 17, 2009
Page 19 of 56
REJ03B0125-0213
3850 Group (Spec.A QzROM version)
INTERRUPTS
Interrupts occur by 15 sources among 15 sources: six external,
eight internal, and one software.
Interrupt Control
Each interrupt is controlled by an interrupt request bit, an
interrupt enable bit, and the interrupt disable flag except for the
software interrupt set by the BRK instruction. An interrupt
occurs if the corresponding interrupt request and enable bits are
“1” and the interrupt disable flag is “0”.
Interrupt enable bits can be set or cleared by software.
Interrupt request bits can be cleared by software, but cannot be
set by software.
The BRK instruction cannot be disabled with any flag or bit. The
I (interrupt disable) flag disables all interrupts except the BRK
instruction interrupt.
When several interrupts occur at the same time, the interrupts are
received according to priority.
Interrupt Operation
By acceptance of an interrupt, the following operations are
automatically performed:
1. The contents of the program counter and the processor sta-
tus register are automatically pushed onto the stack.
2. The interrupt disable flag is set and the corresponding inter-
rupt request bit is cleared.
3. The interrupt jump destination address is read from the vec-
tor table into the program counter.
<Notes>
When setting the followings, the interrupt request bit may be set
to “1”.
When setting external interrupt active edge
Related register: Interrupt edge selection register
(address 003A16)
Timer XY mode register (address 002316)
When switching interrupt sources of an interrupt vector
address where two or more interrupt sources are allocated
Related register: Interrupt edge selection register (address
003A16)
When not requiring for the interrupt occurrence synchronized
with these setting, take the following sequence.
(1) Set the corresponding interrupt enable bit to “0” (disabled).
(2) Set the interrupt edge select bit (the active edge selection
bit) or the interrupt source select.
(3) Set the corresponding interrupt request bit to “0” after 1 or
more instructions have been executed.
(4) Set the corresponding interrupt enable bit to “1” (enabled).
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相关代理商/技术参数
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