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参数资料
| 型号： | M393T5750BY3-CCC |
| 元件分类： | DRAM |
| 英文描述： | 256M X 72 DDR DRAM MODULE, 0.6 ns, DMA240 |
| 封装： | LEAD FREE, DIMM-240 |
| 文件页数： | 12/21页 |
| 文件大小： | 467K |
| 代理商： | M393T5750BY3-CCC |
Rev. 1.3 Aug. 2005
512MB, 1GB, 2GB Registered DIMMs
DDR2 SDRAM
DDR2 Registered DIMM Ordering Information
Note: “Z” and “Y” of Part number(11th digit) stand for Lead-free products.
Note: “3” of Part number(12th digit) stand for Dummy Pad PCB products.
Part Number
Density
Organization
Component Composition
Number of Rank
Height
M393T6553BG(Z)3-CD5/CC
512MB
64Mx72
64Mx8(K4T51083QB)*9EA
1
30mm
M393T6553BG(Z)0-CD5/CC
512MB
64Mx72
64Mx8(K4T51083QB)*9EA
1
30mm
M393T2953BG(Z)3-CD5/CC
1GB
128Mx72
64Mx8(K4T51083QB)*18EA
2
30mm
M393T2953BG(Z)0-CD5/CC
1GB
128Mx72
64Mx8(K4T51083QB)*18EA
2
30mm
M393T2950BG(Z)3-CD5/CC
1GB
128Mx72
128Mx4(K4T51043QB)*18EA
1
30mm
M393T2950BG(Z)0-CD5/CC
1GB
128Mx72
128Mx4(K4T51043QB)*18EA
1
30mm
M393T5750BS(Y)3-CD5/CC
2GB
256Mx72
128Mx4(K4T51043QB)*36EA
2
30mm
M393T5750BS(Y)0-CD5/CC
2GB
256Mx72
128Mx4(K4T51043QB)*36EA
2
30mm
Features
Performance range
JEDEC standard 1.8V ± 0.1V Power Supply
VDDQ = 1.8V ± 0.1V
200 MHz fCK for 400Mb/sec/pin, 267MHz fCK for 533Mb/sec/pin
4 Banks
Posted CAS
Programmable CAS Latency: 3, 4, 5
Programmable Additive Latency: 0, 1 , 2 , 3 and 4
Write Latency(WL) = Read Latency(RL) -1
Burst Length: 4 , 8(Interleave/nibble sequential)
Programmable Sequential / Interleave Burst Mode
Bi-directional Differential Data-Strobe (Single-ended data-strobe is an optional feature)
Off-Chip Driver(OCD) Impedance Adjustment
On Die Termination
Average Refresh Period 7.8us at lower than TCASE 85°C, 3.9us at 85°C < TCASE < 95°C
Serial presence detect with EEPROM
DDR2 SDRAM Package: 60ball FBGA - 128Mx4/64Mx8
All of Lead-free products are compliant for RoHS
Note: For detailed DDR2 SDRAM operation, please refer to Samsung’s Device operation & Timing diagram.
D5(DDR2-533)
CC(DDR2-400)
Unit
Speed@CL3
400
Mbps
Speed@CL4
533
400
Mbps
Speed@CL5
-
-Mbps
CL-tRCD-tRP
4-4-4
3-3-3
CK
Address Configuration
Organization
Row Address
Column Address
Bank Address
Auto Precharge
128Mx4(512Mb) based Module
A0-A13
A0-A9,A11
BA0-BA1
A10
64Mx8(512Mb) based Module
A0-A13
A0-A9
BA0-BA1
A10
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PDF描述 |
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| M3H11TAD | 8 pin DIP, 5.0 or 3.3 Volt, HCMOS/TTL Clock Oscillator |
| M3H12FAD | 8 pin DIP, 5.0 or 3.3 Volt, HCMOS/TTL Clock Oscillator |
| M3H12FBD | 8 pin DIP, 5.0 or 3.3 Volt, HCMOS/TTL Clock Oscillator |
| M3H12TAD | 8 pin DIP, 5.0 or 3.3 Volt, HCMOS/TTL Clock Oscillator |
| M3H13FAD | 8 pin DIP, 5.0 or 3.3 Volt, HCMOS/TTL Clock Oscillator |
相关代理商/技术参数 |
参数描述 |
|---|---|
| M393T5750BY3-CD5/CC | 制造商:SAMSUNG 制造商全称:Samsung semiconductor 功能描述:DDR2 Registered SDRAM MODULE 240pin Registered Module based on 512Mb B-die 72-bit ECC |
| M393T5750CZ3-CCC | 制造商:SAMSUNG 制造商全称:Samsung semiconductor 功能描述:DDR2 Registered SDRAM MODULE 240pin Registered Module based on 512Mb C-die 72-bit ECC |
| M393T5750CZ3-CCC00 | 制造商:Samsung Semiconductor 功能描述:512MSDDDRII_MDDR SDRAM MODULX72BOC(LF) - Bulk |
| M393T5750CZ3-CD5 | 制造商:SAMSUNG 制造商全称:Samsung semiconductor 功能描述:DDR2 Registered SDRAM MODULE 240pin Registered Module based on 512Mb C-die 72-bit ECC |
| M393T5750CZA-CCC | 制造商:SAMSUNG 制造商全称:Samsung semiconductor 功能描述:DDR2 Registered SDRAM MODULE 240pin Registered Module based on 512Mb C-die 72-bit ECC |
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