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参数资料
| 型号： | M393T5750BY3-CCC |
| 元件分类： | DRAM |
| 英文描述： | 256M X 72 DDR DRAM MODULE, 0.6 ns, DMA240 |
| 封装： | LEAD FREE, DIMM-240 |
| 文件页数： | 8/21页 |
| 文件大小： | 467K |
| 代理商： | M393T5750BY3-CCC |
Rev. 1.3 Aug. 2005
512MB, 1GB, 2GB Registered DIMMs
DDR2 SDRAM
Parameter
Symbol
DDR2-533
DDR2-400
Units
Notes
min
max
min
max
DQS falling edge to CK setup time
tDSS
0.2
x
0.2
x
tCK
DQS falling edge hold time from CK
tDSH
0.2
x
0.2
x
tCK
Mode register set command cycle time
tMRD
2
x
2
x
tCK
Write postamble
tWPST
0.4
0.6
0.4
0.6
tCK
Write preamble
tWPRE
0.35
x
0.35
x
tCK
Address and control input hold time
tIH
375
x
475
x
ps
Address and control input setup time
tIS
250
x
350
x
ps
Read preamble
tRPRE
0.9
1.1
0.9
1.1
tCK
Read postamble
tRPST
0.4
0.6
0.4
0.6
tCK
Active to active command period for 1KB page size products
tRRD
7.5
x
7.5
x
ns
Active to active command period for 2KB page size products
tRRD
10
x
10
x
ns
Four Activate Window for 1KB page size products
tFAW
37.5
ns
Four Activate Window for 2KB page size products
tFAW
50
ns
CAS to CAS command delay
tCCD
2
tCK
Write recovery time
tWR
15
x
15
x
ns
Auto precharge write recovery + precharge time
tDAL
tWR+tRP
x
tWR+tRP
x
tCK
Internal write to read command delay
tWTR
7.5
x10
x
ns
Internal read to precharge command delay
tRTP
7.5
ns
Exit self refresh to a non-read command
tXSNR
tRFC + 10
ns
Exit self refresh to a read command
tXSRD
200
tCK
Exit precharge power down to any non-read command
tXP
2
x
2
x
tCK
Exit active power down to read command
tXARD
2
x
2
x
tCK
Exit active power down to read command
(Slow exit, Lower power)
tXARDS
6 - AL
tCK
CKE minimum pulse width
(high and low pulse width)
tCKE
33
tCK
ODT turn-on delay
tAOND
2
tCK
ODT turn-on
tAON
tAC(min)
tAC(max)+1
tAC(min)
tAC(max)+1
ns
ODT turn-on(Power-Down mode)
tAONPD
tAC(min)+2
2tCK+tAC(m
ax)+1
tAC(min)+2
2tCK+tAC
(max)+1
ns
ODT turn-off delay
tAOFD
2.5
tCK
ODT turn-off
tAOF
tAC(min)
tAC(max)+ 0.6
tAC(min)
tAC(max)+ 0.6
ns
ODT turn-off (Power-Down mode)
tAOFPD
tAC(min)+2
2.5tCK+
tAC(max)+1
tAC(min)+2
2.5tCK+
tAC(max)+1
ns
ODT to power down entry latency
tANPD
3
tCK
ODT power down exit latency
tAXPD
8
tCK
OCD drive mode output delay
tOIT
0
12
0
12
ns
Minimum time clocks remains ON after CKE asynchronously drops LOW
tDelay
tIS+tCK +tIH
ns
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相关代理商/技术参数 |
参数描述 |
|---|---|
| M393T5750BY3-CD5/CC | 制造商:SAMSUNG 制造商全称:Samsung semiconductor 功能描述:DDR2 Registered SDRAM MODULE 240pin Registered Module based on 512Mb B-die 72-bit ECC |
| M393T5750CZ3-CCC | 制造商:SAMSUNG 制造商全称:Samsung semiconductor 功能描述:DDR2 Registered SDRAM MODULE 240pin Registered Module based on 512Mb C-die 72-bit ECC |
| M393T5750CZ3-CCC00 | 制造商:Samsung Semiconductor 功能描述:512MSDDDRII_MDDR SDRAM MODULX72BOC(LF) - Bulk |
| M393T5750CZ3-CD5 | 制造商:SAMSUNG 制造商全称:Samsung semiconductor 功能描述:DDR2 Registered SDRAM MODULE 240pin Registered Module based on 512Mb C-die 72-bit ECC |
| M393T5750CZA-CCC | 制造商:SAMSUNG 制造商全称:Samsung semiconductor 功能描述:DDR2 Registered SDRAM MODULE 240pin Registered Module based on 512Mb C-die 72-bit ECC |
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