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参数资料
| 型号： | M393T5750BY3-CCC |
| 元件分类： | DRAM |
| 英文描述： | 256M X 72 DDR DRAM MODULE, 0.6 ns, DMA240 |
| 封装： | LEAD FREE, DIMM-240 |
| 文件页数： | 13/21页 |
| 文件大小： | 467K |
| 代理商： | M393T5750BY3-CCC |
Rev. 1.3 Aug. 2005
512MB, 1GB, 2GB Registered DIMMs
DDR2 SDRAM
CK0
PLL
OUT1
OUTN
Reg.A
Reg.B
Feedback In
Feedback Out
IN
0ns (nominal)
C
120 ohms
C
Note:
1. The clock delay from the input of the PLL clock to the input of any DDR2 SDRAM or register will be set to 0ns (nominal).
2. Input, output, and feedback clock lines are terminated from line to line as shown, and not from line to ground.
3. Only one PLL output is shown per output type. Any additional PLL outputs will be wired in a similar manner.
4. Termination resistors for the PLL feedback path clocks are located as close to the input pin of the PLL as possible.
DDR2 SDRAM
240 Pin DDR2 Registered DIMM Clock Topology
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PDF描述 |
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| M3H12FAD | 8 pin DIP, 5.0 or 3.3 Volt, HCMOS/TTL Clock Oscillator |
| M3H12FBD | 8 pin DIP, 5.0 or 3.3 Volt, HCMOS/TTL Clock Oscillator |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| M393T5750BY3-CD5/CC | 制造商:SAMSUNG 制造商全称:Samsung semiconductor 功能描述:DDR2 Registered SDRAM MODULE 240pin Registered Module based on 512Mb B-die 72-bit ECC |
| M393T5750CZ3-CCC | 制造商:SAMSUNG 制造商全称:Samsung semiconductor 功能描述:DDR2 Registered SDRAM MODULE 240pin Registered Module based on 512Mb C-die 72-bit ECC |
| M393T5750CZ3-CCC00 | 制造商:Samsung Semiconductor 功能描述:512MSDDDRII_MDDR SDRAM MODULX72BOC(LF) - Bulk |
| M393T5750CZ3-CD5 | 制造商:SAMSUNG 制造商全称:Samsung semiconductor 功能描述:DDR2 Registered SDRAM MODULE 240pin Registered Module based on 512Mb C-die 72-bit ECC |
| M393T5750CZA-CCC | 制造商:SAMSUNG 制造商全称:Samsung semiconductor 功能描述:DDR2 Registered SDRAM MODULE 240pin Registered Module based on 512Mb C-die 72-bit ECC |
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