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参数资料
| 型号： | M393T5750BY3-CCC |
| 元件分类： | DRAM |
| 英文描述： | 256M X 72 DDR DRAM MODULE, 0.6 ns, DMA240 |
| 封装： | LEAD FREE, DIMM-240 |
| 文件页数： | 7/21页 |
| 文件大小： | 467K |
| 代理商： | M393T5750BY3-CCC |
Rev. 1.3 Aug. 2005
512MB, 1GB, 2GB Registered DIMMs
DDR2 SDRAM
Electrical Characteristics & AC Timing for DDR2-533/400 SDRAM
(0
°C < TCASE < 95 °C; VDDQ = 1.8V + 0.1V; VDD = 1.8V + 0.1V)
Refresh Parameters by Device Density
Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin
Timing Parameters by Speed Grade
(Refer to notes for informations related to this table at the bottom)
Parameter
Symbol
256Mb
512Mb
1Gb
2Gb
4Gb
Units
Refresh to active/Refresh command time
tRFC
75
105
127.5
195
tbd
ns
Average periodic refresh interval
tREFI
0
°C ≤ TCASE ≤ 85°C
7.8
s
85
°C < TCASE ≤ 95°C
3.9
s
Speed
DDR2-533(D5)
DDR2-400(CC)
Units
Bin (CL - tRCD - tRP)
4 - 4 - 4
3 - 3 - 3
Parameter
min
max
min
max
tCK, CL=3
5
8
5
8
ns
tCK, CL=4
3.75
8
5
8
ns
tCK, CL=5
-
ns
tRCD
15
ns
tRP
15
ns
tRC
55
ns
tRAS
40
70000
40
70000
ns
Parameter
Symbol
DDR2-533
DDR2-400
Units
Notes
min
max
min
max
DQ output access time from CK/CK
tAC
-500
+500
-600
+600
ps
DQS output access time from CK/CK
tDQSCK
-450
+450
-500
+500
ps
CK high-level width
tCH
0.45
0.55
0.45
0.55
tCK
CK low-level width
tCL
0.45
0.55
0.45
0.55
tCK
CK half period
tHP
min(tCL, tCH)
x
min(tCL, tCH)
x
ps
Clock cycle time, CL=x
tCK
3750
8000
5000
8000
ps
DQ and DM input hold time
tDH
225
x275
x
ps
DQ and DM input setup time
tDS
100
x150
x
ps
Control & Address input pulse width for each input
tIPW
0.6
x0.6
x
tCK
DQ and DM input pulse width for each input
tDIPW
0.35
x0.35
x
tCK
Data-out high-impedance time from CK/CK
tHZ
x
tAC max
x
tAC max
ps
DQS low-impedance time from CK/CK
tLZ(DQS)
tAC min
tAC max
tAC min
tAC max
ps
DQ low-impedance time from CK/CK
tLZ(DQ)
2* tACmin
tAC max
2* tACmin
tAC max
ps
DQS-DQ skew for DQS and associated DQ signals
tDQSQ
x
300
x
350
ps
DQ hold skew factor
tQHS
x
400
x
450
ps
DQ/DQS output hold time from DQS
tQH
tHP - tQHS
x
tHP - tQHS
x
ps
Write command to first DQS latching transition
tDQSS
WL-0.25
WL+0.25
WL-0.25
WL+0.25
tCK
DQS input high pulse width
tDQSH
0.35
x
0.35
x
tCK
DQS input low pulse width
tDQSL
0.35
x
0.35
x
tCK
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相关代理商/技术参数 |
参数描述 |
|---|---|
| M393T5750BY3-CD5/CC | 制造商:SAMSUNG 制造商全称:Samsung semiconductor 功能描述:DDR2 Registered SDRAM MODULE 240pin Registered Module based on 512Mb B-die 72-bit ECC |
| M393T5750CZ3-CCC | 制造商:SAMSUNG 制造商全称:Samsung semiconductor 功能描述:DDR2 Registered SDRAM MODULE 240pin Registered Module based on 512Mb C-die 72-bit ECC |
| M393T5750CZ3-CCC00 | 制造商:Samsung Semiconductor 功能描述:512MSDDDRII_MDDR SDRAM MODULX72BOC(LF) - Bulk |
| M393T5750CZ3-CD5 | 制造商:SAMSUNG 制造商全称:Samsung semiconductor 功能描述:DDR2 Registered SDRAM MODULE 240pin Registered Module based on 512Mb C-die 72-bit ECC |
| M393T5750CZA-CCC | 制造商:SAMSUNG 制造商全称:Samsung semiconductor 功能描述:DDR2 Registered SDRAM MODULE 240pin Registered Module based on 512Mb C-die 72-bit ECC |
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