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参数资料
| 型号： | M66290AGP |
| 元件分类： | 总线控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQFP48 |
| 封装： | LQFP-48 |
| 文件页数： | 24/54页 |
| 文件大小： | 452K |
| 代理商： | M66290AGP |
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USB DEVICE CONTROLLER
M66290AGP/FP
MITSUBISHI <DIGITAL ASSP>
29
Construction of endpoint (EP1 to EP5) FIFO
Transfer type
EPi_TYP[1:0]
Can be set to Bulk,
Interrupt, isochronous
transfer.
Transfer direction
EPi_DIR
Can be set to IN/OUT
Double buffer
(Toggle buffer)
EPi_DBLB
Can be set
Continuous
transmit/receive
EPi_RWMD
Can be set
(Effective in bulk transfer)
Buffer size
EPi_Buf_siz[3:0]
Can be set
(Up to 1024bytes by
a unit of 64bytes)
Response PID
EPi_PID[1:0]
Can be set to
NAK, STALL, and
BUF(buffer control).
DMA transfer
EPi_DMAE
Can be set
Receive data
read and abandon
mode
EPi_ACLR
Can be set
Max packet size
EPi_MXPS[9:0]
Can be set
( 0 to 1023bytes)
Register
EP1 to EP5
Examples of endpoint FIFO setting
FIFO
number
Memory
address
Endpoint setting
00h to
03h
000h to
0FFh
EP0:Control write transfer
Buffer size:256Bytes
Control write continuous receive
mode(CTRW)
FIFO area:256Bytes(4 blocks)
04h to
07h
100h to
1FFh
EP0:Control read transfer
Buffer size:256Bytes
Control read continuous transmit
mode(CTRR)
FIFO area:256Bytes(4 blocks)
08h
200h to
23Fh
EP2:Interrupt transfer(IN)
Buffer size:64Bytes
FIFO area:64Bytes(1 block)
09h
240h to
27Fh
EP4:Interrupt transfer(OUT)
Buffer size:64Bytes
FIFO area:64Bytes(1 block)
0Ah to
0Bh
280h to
2FFh
EP3:Bulk transfer(IN)
Buffer size:64Bytes
Double buffer constitution(DBLB)
FIFO area:128Bytes(2 blocks)
0Ch to
0Fh
300h to
3FFh
Not used:256Bytes(4 blocks)
10h to
2Fh
400h to
BFFh
EP1:Bulk transfer(OUT)
Buffer size:1024Bytes
Double buffer constitution(DBLB)
Continuous receive mode(RWMD)
FIFO area:2kBytes(32 blocks)
(4) Endpoint and FIFO control
Except f or EP0 f or control transf er, M66290A can set
f iv e endpoints as EP1 to EP5.
Each of these f iv e endpoints (EP1 to EP5) can be set to
bulk, interrupt, and isochronous transf er. And y et,
another constitution can conf igurated independently.
Below are the constitutions to be realized.
Built-in FIFO f or endpoint buff er is 3kBy tes totally of its
memory c apacity . This FIFO of 3kBy tes can div ided
into each endpoint of EP0 to EP5 and to each endpoint,
can assign up to 1024By tes (max) by a unit of 64By tes.
Buff er size of each endpoint must be set to ov er the
capacity which is set in maximum buff er size.
In the buff er size, which is set, by tes of m aximum
packet size is used f or v alid. (If set the buff er size to
128By tes to the endpoint which maximum packet size
is set to 64By tes, 64By tes are v alid)
We show setting examples to each of these buff er of
EP0 to EP5 below, and next explain about continuous
transmit and receiv e f unction, FIFO control, DMA
transf er, and double buff er.
Continuous transfer function
Continuous transf er f unction is to transmit/receiv e data
which extend plural transaction without occurring interrupt
to CPU.
For EP1 to EP5, this f unction is eff ectiv e when transf er
ty pe is bulk transf er.
In each endpoint, when continuous transf er mode is set,
it can transf er data up to the buff er size which is set to
the endpoint without occurring interrupt to CPU.
To use with double buff er constitution, 1kBy tes x2
maximum of buff ering is realized.
Continuous receiv e mode can receiv e data packet
continuously up to the buff er size which is set, or until
receiv es short packet. If the data to be receiv ed is data
packet of m ax packet size, it can receiv e continuously
up to the buff er size without occurring interrupt to CPU,
and if the data is data packet (max packet size) which is
less than buff er size, interrupt to CPU is not occurred.
In bulk transf er, when set max packet size as 64By tes,
buff er size as 1024By tes, and FIFO constitution as
double buff er, when receiv ed data of m ax packet size
as 16 times (1024By tes), it became buff er redried
enable) and urge to CPU by interrupt to read receiv ed
data. When receiv ed short packet, ends the continuous
receiv e and buff er became redried enable).
Continuous transmit mode can transmit data packet
continuously up to buff er size which is set. Short packet
transmit can be done to set IVAL f lag. And it is needed
to set IVAL f lag to transmit a multiple data of m aximum
packet size which is less than buff er size.
By set Null data transmit addition mode, when write a
multiple data of max packet size into buff er and
transmit, Null data can be transmitted automatically
af ter the last packet is transmitted .
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相关代理商/技术参数 |
参数描述 |
|---|---|
| M66291GP | 制造商:Renesas Electronics Corporation 功能描述: |
| M66291GP#201 | 制造商:Renesas Electronics Corporation 功能描述:IC ASSP USB2.0 DEVICE CONTROLLER 48LQFP |
| M66291GP#RB0S | 功能描述:IC USB CONTROLLER GEN-PUR 48LQFP RoHS:是 类别:集成电路 (IC) >> 接口 - 控制器 系列:- 标准包装:4,900 系列:- 控制器类型:USB 2.0 控制器 接口:串行 电源电压:3 V ~ 3.6 V 电流 - 电源:135mA 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:36-VFQFN 裸露焊盘 供应商设备封装:36-QFN（6x6） 包装:* 其它名称:Q6396337A |
| M66291GPRB0S | 制造商:Renesas Electronics Corporation 功能描述:USB2.0 Device Controller,LQFP48 |
| M66291HP | 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:ASSP (USB2.0 Device Controller) |
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