- 您现在的位置：买卖IC网 > PDF目录379298 > M68HC05M68H (Motorola, Inc.) HCMOS Microcontroller Unit PDF资料下载
参数资料
| 型号： | M68HC05M68H |
| 厂商： | Motorola, Inc. |
| 英文描述： | HCMOS Microcontroller Unit |
| 中文描述： | HCMOS微控制器 |
| 文件页数： | 48/130页 |
| 文件大小： | 1541K |
| 代理商： | M68HC05M68H |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页当前第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页第127页第128页第129页第130页
Interrupts
Advance Information
MC68HC705P6A
—
Rev. 2.0
48
Interrupts
MOTOROLA
5.3.1 Reset Interrupt Sequence
The reset function is not in the strictest sense an interrupt; however, it is
acted upon in a similar manner as shown in
Figure 5-1
. A low-level input
on the RESET pin or internally generated RST signal causes the
program to vector to its starting address which is specified by the
contents of memory locations $1FFE and $1FFF. The I bit in the
condition code register is also set. The MCU is configured to a known
state during this type of reset as previously described in
Section 4.
Resets
.
5.3.2 Software Interrupt (SWI)
The SWI is an executable instruction. It is also a non-maskable interrupt
since it is executed regardless of the state of the I bit in the CCR. As with
any instruction, interrupts pending during the previous instruction will be
serviced before the SWI opcode is fetched. The interrupt service routine
address for the SWI instruction is specified by the contents of memory
locations $1FFC and $1FFD.
5.3.3 Hardware Interrupts
All hardware interrupts are maskable by the I bit in the CCR. If the I bit is
set, all hardware interrupts (internal and external) are disabled. Clearing
the I bit enables the hardware interrupts. Four hardware interrupts are
explained in the following subsections.
5.3.3.1 External Interrupt (IRQ)
The IRQ/V
PP
pin drives an asynchronous interrupt to the CPU. An edge
detector flip-flop is latched on the falling edge of IRQ/V
PP
. If either the
output from the internal edge detector flip-flop or the level on the
IRQ/V
PP
pin is low, a request is synchronized to the CPU to generate the
IRQ interrupt. If the LEVEL bit in the mask option register is clear (edge-
sensitive only), the output of the internal edge detector flip-flop is
sampled and the input level on the IRQ/V
PP
pin is ignored. The interrupt
service routine address is specified by the contents of memory locations
相关PDF资料 |
PDF描述 |
|---|---|
| M68HC11K | 8-BIT MICROCONTROLLER |
| M68HC711CFD | CONFIG REGISTER PROGRAMMING FOR EEPROM-BASED MHC MICROCONTROLLERS |
| M68HC711CFG | CONFIG REGISTER PROGRAMMING FOR EEPROM-BASED MHC MICROCONTROLLERS |
| M68SDIL12 | The MC68HC912DT128A microcontroller unit (MCU) is a 16-bit device composed of standard on-chip peripherals including a 16-bit central processing unit |
| M68ADP912DG128PV | The MC68HC912DT128A microcontroller unit (MCU) is a 16-bit device composed of standard on-chip peripherals including a 16-bit central processing unit |
相关代理商/技术参数 |
参数描述 |
|---|---|
| M68HC08 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:Microcontrollers |
| M68HC08M6 | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:HCMOS Microcontroller Unit |
| M68HC08M68H | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:HCMOS Microcontroller Unit |
| M68HC11 | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:CONFIG Register Programming for EEPROM-based M68HC11 Microcontrollers |
| M68HC11_03 | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:8-channel, 8-bit analog-to-digital (A/D) converter |
发布紧急采购，3分钟左右您将得到回复。