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| 型号： | M68HC05M68H |
| 厂商： | Motorola, Inc. |
| 英文描述： | HCMOS Microcontroller Unit |
| 中文描述： | HCMOS微控制器 |
| 文件页数： | 64/130页 |
| 文件大小： | 1541K |
| 代理商： | M68HC05M68H |
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Serial Input/Output Port (SIOP)
Advance Information
MC68HC705P6A
—
Rev. 2.0
64
Serial Input/Output Port (SIOP)
MOTOROLA
cleared by reading the SSR followed by a read or write of the SDR. If
the SPIF is cleared before the last rising edge of SCK, it will be set
again on the last rising edge of SCK. Reset clears the SPIF bit.
DCOL
—
Data Collision
DCOL is a read-only status bit which indicates that an illegal access
of the SDR has occurred. The DCOL bit will be set when reading or
writing the SDR after the first falling edge of SCK and before SPIF is
set. Reading or writing the SDR during this time will result in invalid
data being transmitted or received.
The DCOL bit is cleared by reading the SSR (when the SPIF bit is set)
followed by a read or write of the SDR. If the last part of the clearing
sequence is done after another transfer has started, the DCOL bit will
be set again. Reset clears the DCOL bit.
7.4.3 SIOP Data Register (SDR)
This register is located at address $000C and serves as both the
transmit and receive data register. Writing to this register will initiate a
message transmission if the SIOP is in master mode. The SIOP
subsystem is not double buffered and any write to this register will
destroy the previous contents. The SDR can be read at any time;
however, if a transfer is in progress, the results may be ambiguous and
the DCOL bit will be set. Writing to the SDR while a transfer is in
progress can cause invalid data to be transmitted and/or received.
Figure 7-5
shows the position of each bit in the register. This register is
not affected by reset.
Address:
$000C
Bit 7
6
5
4
3
2
1
Bit 0
Read:
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0
Write:
Reset:
Unaffected by reset
Figure 7-5. Serial Port Data Register (SDR)
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