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| 型号： | M68HC05M68H |
| 厂商： | Motorola, Inc. |
| 英文描述： | HCMOS Microcontroller Unit |
| 中文描述： | HCMOS微控制器 |
| 文件页数： | 63/130页 |
| 文件大小： | 1541K |
| 代理商： | M68HC05M68H |
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Serial Input/Output Port (SIOP)
SIOP Registers
MC68HC705P6A
—
Rev. 2.0
Advance Information
MOTOROLA
Serial Input/Output Port (SIOP)
63
will 1) abort the transmission, 2) reset the serial bit counter, and 3)
convert the port B/SIOP port to a general-purpose I/O port. Reset
clears the SPE bit.
MSTR
—
Master Mode Select
When set, the MSTR bit configures the serial I/O port for master
mode. A transfer is initiated by writing to the SDR. Also, the SCK pin
becomes an output providing a synchronous data clock dependent
upon the oscillator frequency. When the device is in slave mode, the
SDO and SDI pins do not change function. These pins behave exactly
the same in both the master and slave modes.
The MSTR bit is readable and writeable at any time regardless of the
state of the SPE bit. Clearing the MSTR bit will abort any transfers that
may have been in progress. Reset clears the MSTR bit as well as the
SPE bit, disabling the SIOP subsystem.
7.4.2 SIOP Status Register (SSR)
This register is located at address $000B and contains two bits.
Figure
7-4
shows the position of each bit in the register and indicates the value
of each bit after reset.
SPIF
—
Serial Port Interface Flag
SPIF is a read-only status bit that is set on the last rising edge of SCK
and indicates that a data transfer has been completed. It has no effect
on any future data transfers and can be ignored. The SPIF bit is
Address:
$000B
Bit 7
6
5
4
3
2
1
Bit 0
Read:
SPIF
DCOL
0
0
0
0
0
0
Write:
Reset:
0
0
0
0
0
0
0
0
= Unimplemented
Figure 7-4. SIOP Status Register (SSR)
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