参数资料
型号: M69AW024B
厂商: 意法半导体
英文描述: 16 Mbit (1M x16) 3V Asynchronous PSRAM
中文描述: 16兆位(1米× 16)3V的异步移动存储芯片
文件页数: 18/29页
文件大小: 429K
代理商: M69AW024B
M69AW024B
18/29
Note: 1. The minimum value must be equal to or greater than the sum of actual t
ELEH
(or t
WLWH
).
2. The new write address is valid from either E1 High or W High.
3. t
AXGL1
is specified from end of t
AVAX
(Min) and is a reference value when access time is determined by t
AXGL1
. If actual value is
lower than specified minimum value, t
AXGL1
is increased by the difference between the actual value and the specified minimum
value.
4. t
AXGL1
maximum is applicable if E1 is kept Low and both W and G are kept High.
5. t
AXGL2
is the absolute minimum value if the Write cycle terminates with W and E1 Low.
6. t
GHEL
(Min) must be kept if the Read cycle is not performed prior to the Write cycle. In case G is disabled after a time t
GHEL
(Min),
W must go Low t
ELEH2
(Min) after E1 goes Low. In other words, the Read cycle is initiated if t
GHEL
(Min) is not kept.
7. Applicable if E1 stays Low after the Read cycle.
8. t
ELEH
or t
WLWH
is applicable if the Write operation is initiated by E1 or W, respectively.
9. If the write operation is terminated by W followed by E1 High, the sum of actual t
ELWL
and t
WLWH
and the sum of actual t
AVWL
and
t
WLWH
must be equal or greater than 60ns.
10. t
EHEL1
or t
WHWL
is applicable if the Write operation is terminated by E1 or W, respectively. If E1 goes High before t
WHWL
(Min), then
t
EHEL1
(Min) must apply.
11. t
EHEL1
and t
EHEL2
is applicable if write operation is terminated by E1 and W, respectively. In case E1 is brought to High before sat-
isfaction of t
EHEL2
(min), the t
EHEL1
(min) is also applied.
12. For other timings please refer to
Table 7., Read and Standby Modes AC Characteristics
.
t
WLEL
t
WS
Write Enable Low Set-up Time
0
0
ns
t
WLWH(1,8)
t
WP
Write Enable Write Pulse Width
45
50
ns
t
WLWL
t
WC
Write Enable Write Cycle Time
80
90
ns
Symbol
Alt.
Parameter
M69AW024B
Unit
–60
–70
Min
Max
Min
Max
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