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参数资料
| 型号： | M69AW048BL70ZB8 |
| 厂商： | 意法半导体 |
| 英文描述： | 32 Mbit (2M x16) 3V Asynchronous PSRAM |
| 中文描述： | 32兆位（200万× 16）3V的异步移动存储芯片 |
| 文件页数： | 9/29页 |
| 文件大小： | 433K |
| 代理商： | M69AW048BL70ZB8 |
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M69AW048B
set to ‘0000h’, and the data of the fifth cycle is the
Power-Down Configuration data (see
Table
5., Power-Down Configuration Data
). If the fourth
cycle is written into a different address, the se-
quence is aborted. In the last cycle, a read is made
from the specific Power-Down Configuration
ad-
dress (see
Table 6., Power-Down Configuration
Addresses
). The Power-Down Configuration data
and address must correspond, otherwise the se-
quence is aborted.
When this sequence is performed to take the de-
vice from one PAR mode to another, the write data
may be lost. So, if a PAR mode is used, this se-
quence should be performed prior to any normal
read or write operations.
Table 2. Operating Modes
Note: X = V
IH
or V
IL
.
1. Should not be kept in this logic condition for a period longer than 1μs.
2. Power-Down mode can be entered from Standby state and all DQ pins are in High-Z state. The Power-Down current and data re-
tention depend on the selection of Power-Down programming.
3. G can be V
IL
during the Write operation if the following conditions are satisfied:
a. Write pulse is initiated by E1 (E1 Controlled Write timing), or cycle time of the previous operation cycle is satisfied;
b. G stays V
IL
during the entire Write cycle.
Table 3. Power-Down Modes
Operation
E1
E2
W
G
LB
UB
DQ0-DQ7
DQ8-DQ15
Power
Standby (Deselected)
V
IH
V
IH
X
X
X
X
Hi-Z
Hi-Z
Standby (I
SB
)
Power-Down
(2)
X
V
IL
X
X
X
X
Hi-Z
Hi-Z
Power-Down
(I
CCPD,
I
CCP4,
I
CCP8,
I
CCP16
)
No Read
(1)
V
IL
V
IH
V
IH
V
IL
V
IH
V
IH
Hi-Z
Hi-Z
Output Disable
Lower Byte Read
(1)
V
IL
V
IH
V
IH
V
IL
V
IL
V
IH
Data Output
Hi-Z
Active (I
CC
)
Lower Byte Write
(1)
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
Data Input
Hi-Z
Active (I
CC
)
No Write
V
IL
V
IH
V
IL
V
IH
V
IH
V
IH
Hi-Z
Hi-Z
Output Disable
Upper Byte Read
(1)
V
IL
V
IH
V
IH
V
IL
V
IH
V
IL
Hi-Z
Data Output
Active (I
CC
)
Upper Byte Write
(1)
V
IL
V
IH
V
IL
V
IH
V
IH
V
IL
Hi-Z
Data Input
Active (I
CC
)
Word Read
(1)
V
IL
V
IH
V
IH
V
IL
V
IL
V
IL
Data Output
Data Output
Active (I
CC
)
Word Write
(1)
V
IL
V
IH
V
IL
V
IH(3)
V
IL
V
IL
Data Input
Data Input
Active (I
CC
)
Mode
Data Retention
Retention Address
Deep Power-Down (Default)
No
N/A
4Mb PAR
4 Mbit
00000h – 3FFFFh
8Mb PAR
8 Mbit
00000h – 7FFFFh
16Mb PAR
16 Mbit
00000h – FFFFFh
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