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参数资料
| 型号： | M7010R-066ZA1T |
| 厂商： | 意法半导体 |
| 英文描述： | 16K x 68-bit Entry NETWORK SEARCH ENGINE |
| 中文描述： | 16K的× 68位进入网络搜索引擎 |
| 文件页数： | 16/67页 |
| 文件大小： | 449K |
| 代理商： | M7010R-066ZA1T |
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M7010R
16/67
OPERATION
Command Bus and DQ Bus
CMD[8:0] carries the command and its associated
parameter. DQ[67:0] is used for data transfer to,
and from the data base entries. The database en-
tries are comprised of a data field and a mask field
which are organized as a data array and a mask
array. The DQ Bus carries the SEARCH data dur-
ing the SEARCH command as well as the address
and data during Pipelined I/O (PIO) READ/WRITE
operations, of the data array, mask array, and in-
ternal registers. The DQ Bus also can carry the ad-
dress information for the PIO accesses to the
SRAM.
Database Entry (Data Array and Mask Array)
Each database entry comprises a data field and a
mask field. The resultant value of the entry is a log-
ical AND of the corresponding data and mask bits
and can take logical values of '1,' '0' and 'X' (don
’
t
care), depending on the value in the mask bit. The
on-chip priority encoder selects the first matching
entry in the database which is nearest to location
0.
Arbitration Logic
When multiple (Silicon) Search Engines are cas-
caded to create large databases, the data being
searched is presented to all Search processors si-
multaneously in the cascaded system. When more
than one device has duplicate entries, the arbitra-
tion logic on the Search Engine with the matching
entry which is closest to address 0 of the cascaded
database, will be selected to drive the SRAM Bus.
Pipeline and SRAM Control
Pipeline latency is added to give enough time to
the arbitration logic in a cascaded system to deter-
mine the index with the highest priority. The pipe-
line logic adds latency to the SRAM access cycles
and the SSF and SSV signals to align them to the
host ASIC receiving the associated data. Refer to
Table 27, page 36 for details.
Full Logic
Bit[0] in each of the 68-bit entries has a special
purpose for the LEARN command (0 = empty, 1 =
full). When all the data entries have Bit[0] set to '1,'
the database asserts the FULL flag, indicating that
all the Search Engines in the depth-cascaded ar-
ray are full.
Connections Descriptions
Master Clock (CLK2X).
The M7010R samples
all of the control and data signals on the positive
edge of CLK2X when PHS_L is low.
Phase (PHS_L).
This signal runs at half the fre-
quency of CLK2X and generates an internal clock
from CLK2X (see Figure 12, page 18).
Reset (RST_L).
Driving RST low initializes the
device to a known state.
Command Bus (CMD[8:0].
[1:0]
command; [8:2] contains the command parame-
ters. The descriptions of individual commands ex-
plains the details of the parameters. The encoding
of commands based on the [1:0] field are:
–
00: PIO READ
–
01: PIO WRITE
–
10: SEARCH
–
11: LEARN
Command Valid (
CMDV)
.
Qualifies the CMD bus
as follows:
–
0: No Command
–
1: Command
Address/Data Bus (
DQ[67:0])
.
Carries the READ
and WRITE address as well as the data during
register, data, and mask array operations. It car-
ries the compare data during SEARCH opera-
tions. It also carries the SRAM address during
SRAM PIO accesses.
READ Acknowledge (ACK).
Indicates that valid
data is available on the DQ Bus during register,
data, and mask array READ operations, or the
data is available on the SRAM data bus during
SRAM READ operations.
Note:
ACK Signals require a pull-down resistor of
47
.
End of Transfer (EOT).
Indicates
burst transfer during READ or WRITE burst oper-
ations.
Note:
EOT Signals require a pull-down resistor of
47 ohms.
SEARCH Successful Flag (SSF).
When assert-
ed, this signal indicates that the device is the glo-
bal winner in a SEARCH operation.
SEARCH Successful Flag Valid (SSV).
When
asserted, this signal qualifies the SSF signal.
SRAM Address (SADR[21:0]).
This
tains address lines to access off-chip SRAMs that
contain associative data. See Table 35, page 61
for the details of the generated SRAM address.
SRAM Chip Enable (CE_L).
This is Chip Enable
control for external SRAMs. When more than one
device is cascaded, CE_L of all devices must be
connected.
SRAM WRITE Enable (WE_L).
This is WRITE
Enable control for external SRAMs. When more
than one device is cascaded, WE_L of all devices
must be connected.
SRAM Output Enable (OE_L).
This
Enable control for external SRAMs. Only the last
device drives this signal (with the LRAM Bit set).
specifies
the
the
end
of
bus
con-
is
Output
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