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参数资料
| 型号： | M95256-RDW3/A |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | PROM |
| 英文描述： | 32K X 8 SPI BUS SERIAL EEPROM, PDSO8 |
| 封装： | 0.169 INCH, TSSOP-8 |
| 文件页数： | 14/43页 |
| 文件大小： | 431K |
| 代理商： | M95256-RDW3/A |
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M95256, M95256-W, M95256-R
Instructions
21/42
5.6
Write to Memory Array (WRITE)
As shown in Figure 10, to send this instruction to the device, Chip Select (S) is first driven
Low. The bits of the instruction byte, address byte, and at least one data byte are then
shifted in, on Serial Data Input (D).
The instruction is terminated by driving Chip Select (S) High at a byte boundary of the input
data. In the case of Figure 10, this occurs after the eighth bit of the data byte has been
latched in, indicating that the instruction is being used to write a single byte. The self-timed
the end of which the Write in Progress (WIP) bit is reset to 0.
If, though, Chip Select (S) continues to be driven Low, as shown in Figure 11, the next byte
of input data is shifted in, so that more than a single byte, starting from the given address
towards the end of the same page, can be written in a single internal Write cycle.
Each time a new data byte is shifted in, the least significant bits of the internal address
counter are incremented. If the number of data bytes sent to the device exceeds the page
boundary, the internal address counter rolls over to the beginning of the page, and the
previous data there are overwritten with the incoming data. (The page size of these devices
is 64 bytes).
The instruction is not accepted, and is not executed, under the following conditions:
●
if the Write Enable Latch (WEL) bit has not been set to 1 (by executing a Write Enable
instruction just before)
●
if a Write cycle is already in progress
●
if the device has not been deselected, by Chip Select (S) being driven High, at a byte
boundary (after the eighth bit, b0, of the last data byte that has been latched in)
●
if the addressed page is in the region protected by the Block Protect (BP1 and BP0)
bits.
Figure 10. Byte Write (WRITE) Sequence
1.
The most significant address bit (b15) is Don’t Care.
C
D
AI01795D
S
Q
15
2
1
3456789 10
20 21 22 23 24 25 26 27
14 13
3210
28 29 30
High Impedance
Instruction
16-Bit Address
0
765432
0
1
Data Byte
31
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| MA-306-29.4912M-K0 | QUARTZ CRYSTAL RESONATOR, 29.4912 MHz |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| M95256RDW3G | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:256 Kbit serial SPI bus EEPROM with high-speed clock |
| M95256-RDW3G | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:256Kbit and 128Kbit Serial SPI Bus EEPROM With High Speed Clock |
| M95256-RDW3G/A | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:256 Kbit Serial SPI bus EEPROM with high speed clock |
| M95256-RDW3G/K | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:256 Kbit serial SPI bus EEPROM with high-speed clock |
| M95256-RDW3G/V | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:256 Kbit Serial SPI bus EEPROM with high speed clock |
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